SLWS224E August   2010  – January 2016 TRF372017

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Recommended Operating Conditions
    3. 6.3 Thermal Information
    4. 6.4 Electrical Characteristics
    5. 6.5 Timing Requirements - SPI: Writing Phase
    6. 6.6 Timing Requirements - SPI: Read-Back Phase
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Integer and Fractional Mode Selection
      2. 7.3.2  Description of PLL Structure
        1. 7.3.2.1 Selecting PLL Divider Values
        2. 7.3.2.2 Setup Example for Integer Mode
        3. 7.3.2.3 Setup Example for Fractional Mode
      3. 7.3.3  Fractional Mode Setup
      4. 7.3.4  Selecting the VCO and VCO Frequency Control
      5. 7.3.5  External VCO
      6. 7.3.6  VCO Test Mode
      7. 7.3.7  Lock Detect
      8. 7.3.8  Tx Divider
      9. 7.3.9  LO Divider
      10. 7.3.10 Mixer
      11. 7.3.11 Disabling Outputs
      12. 7.3.12 Power Supply Distribution
      13. 7.3.13 Carrier Feedthrough Cancellation
      14. 7.3.14 Internal Baseband Bias Voltage Generation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Powersave Mode
    5. 7.5 Register Maps
      1. 7.5.1 Serial Interface Programming Registers Definition
        1. 7.5.1.1 PLL SPI Registers
          1. 7.5.1.1.1 Register 1
          2. 7.5.1.1.2 Register 2
          3. 7.5.1.1.3 Register 3
          4. 7.5.1.1.4 Register 4
          5. 7.5.1.1.5 Register 5
          6. 7.5.1.1.6 Register 6
          7. 7.5.1.1.7 Register 7
        2. 7.5.1.2 Readback Mode
          1. 7.5.1.2.1 Readback From the Internal Registers Banks
            1. 7.5.1.2.1.1 Register 0 Write
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 DAC Interfacing With External Baseband Bias Voltage
        2. 8.2.2.2 DAC Interface Using Internal VCM Generation
        3. 8.2.2.3 LO Outputs
        4. 8.2.2.4 Loop Filter
        5. 8.2.2.5 ESD Sensitivity
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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订购信息

5 Pin Configuration and Functions

RGZ Package
48-Pin VQFN
Top View
TRF372017 po_lws221.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
BBI_P 27 I Base-band in-phase input: positive terminal. Internal 5 kΩ to VCM generator. If VCM is internally generated (PWD_BB_VCM = 0), external AC coupling caps and 100-Ω differential termination to BBI_N is required.
BBI_N 28 I Base-band in-phase input: negative terminal. Internal 5 kΩ to VCM generator. If VCM is internally generated (PWD_BB_VCM = 0), external AC coupling caps and 100-Ω differential termination to BBI_P is required.
BBQ_N 9 I Base-band in-quadrature input: negative terminal. Internal 5 kΩ to VCM generator. If VCM is internally generated (PWD_BB_VCM = 0), external AC coupling caps and 100-Ω differential termination to BBQ_P is required.
BBQ_P 10 I Base-band in-quadrature input: positive terminal. Internal 5 kΩ to VCM generator. If VCM is internally generated (PWD_BB_VCM = 0), external AC coupling caps and 100-Ω differential termination to BBQ_N is required.
CLK 47 I SPI clock input. Digital input. High impedance.
CP_OUT 40 O Charge pump output
DATA 46 I SPI data input. Digital input. High impedance.
EXT_VCO 36 I External local oscillator input. High impedance. Normally AC-coupled.
GND 6, 8, 11, 12, 13, 15, 16, 17, 19, 22, 23, 24, 25, 26, 29, 31, 37, 39, 42, 44 — Ground
GND_DIG 4 — Digital ground
LD 5 O PLL lock detect output, as configured by MUX_CTRL. Digital output pins can source or sink up to 8 mA of current.
LE 45 I SPI latch enable. Digital input. High impedance.
LO_OUT_N 33 O Local oscillator output: negative terminal. Open collector output. A pullup is required. Normally AC-coupled.
LO_OUT_P 34 O Local oscillator output: positive terminal. Open collector output. A pullup is required. Normally AC-coupled.
PS 1 I Power saving mode enable (Low = normal mode; High = power saving mode)
RDBK 2 O SPI internal registers readback output. Digital output pins can source or sink up to 8 mA of current.
REFIN 43 I Reference clock input. High impedance. Normally AC-coupled.
RFOUT 18 O RF output. Internally matched to 50-Ω output. Normally AC-coupled.
RSVD 14 — Reserved. Normally open.
SCAN_EN 48 I Internal testing mode digital input. Connect to ground in normal operation
VCC_D2S 20 — 5-V modulator output buffer power supply
VCC_DIG 3 — 3.3-V digital power supply
VCC_LO1 7 — 3.3-V Tx path local oscillator chain power supply
VCC_LO2 30 — 3.3-V output local oscillator chain power supply
VCC_MIX 21 — 5-V modulator power supply
VCC_PLL 41 — 3.3-V PLL power supply
VCC_VCO1 35 — 3.3-V VCO power supply
VCC_VCO2 32 — 3.3-V to 5-V VCO power supply
VTUNE 38 I VCO control voltage input