ZHCSN72 june   2023 TPSI2072-Q1

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. Revision History
  6. Pin Configuration and Functions
    1. 5.1 Pin Functions
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Avalanche Robustness
    4. 8.4 Device Functional Modes
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Dielectric Withstand Testing (HiPot)
      2. 9.2.2 Design Requirements
      3. 9.2.3 Design Procedure - Chassis Ground Reference
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 接收文档更新通知
    2. 10.2 支持资源
    3. 10.3 Trademarks
    4. 10.4 静电放电警告
    5. 10.5 术语表
  12. 11Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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订购信息

Overview

The TPSI2072-Q1 is a two channel isolated solid state relay designed for high voltage automotive and industrial applications. TI's high reliability capacitive isolation technology in combination with back-to-back MOSFETs form a completely integrated solution requiring no secondary side power supply.

As seen in the Functional Block Diagram, the primary side consists of two drivers which deliver power and enable logic information to each of the internal MOSFETs on the secondary side. The on-board oscillator controls the frequency of the drivers' operation and the Spread Spectrum Modulation (SSM) controller varies the driver frequency to improve system EMI performance. When one or both of the enable pins are brought HI and the VDD voltage is above the UVLO threshold, the oscillator starts and the drivers send power and a logic HI across the barrier. When one or both of the enable pins are brought LO or the VDD voltage falls below the UVLO threshold, the corresponding driver or drivers are disabled. The lack of activity communicates a logic LO to the secondary side and the MOSFETs are disabled.

Each MOSFET on the secondary side has a dedicated full-bridge rectifier to form its local power supply and a receiver. The receiver determines the logic state delivered from the primary side through the capacitive isolation barrier and uses a slew rate controlled driver to drive the MOSFET's gate. Each receiver performs signal conditioning on the signals received across the barrier in order to filter common mode interference and ensure that the MOSFETs are controlled according to the logic sent by the primary side driver and the system.

The avalanche robust MOSFETs and the thermal benefits of the widened pins on the 11 DWQ package enable the TPSI2072-Q1 to support dielectric withstand testing (HiPot) and DC fast charger surge currents of up to 2 mA without requiring any external protection components.