ZHCSOF4A February   2022  – September 2022 TPS7H5005-SEP , TPS7H5006-SEP , TPS7H5007-SEP , TPS7H5008-SEP

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: All Devices
    6. 7.6  Electrical Characteristics: TPS7H5005-SEP
    7. 7.7  Electrical Characteristics: TPS7H5006-SEP
    8. 7.8  Electrical Characteristics: TPS7H5007-SEP
    9. 7.9  Electrical Characteristics: TPS7H5008-SEP
    10. 7.10 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VIN and VLDO
      2. 8.3.2  Start-Up
      3. 8.3.3  Enable and Undervoltage Lockout (UVLO)
      4. 8.3.4  Voltage Reference
      5. 8.3.5  Error Amplifier
      6. 8.3.6  Output Voltage Programming
      7. 8.3.7  Soft Start (SS)
      8. 8.3.8  Switching Frequency and External Synchronization
        1. 8.3.8.1 Internal Oscillator Mode
        2. 8.3.8.2 External Synchronization Mode
        3. 8.3.8.3 Primary-Secondary Mode
      9. 8.3.9  Primary Switching Outputs (OUTA/OUTB)
      10. 8.3.10 Synchronous Rectifier Outputs (SRA/SRB)
      11. 8.3.11 Dead Time and Leading Edge Blank Time Programmability (PS, SP, and LEB)
      12. 8.3.12 Pulse Skipping
      13. 8.3.13 Duty Cycle Programmability
      14. 8.3.14 Current Sense and PWM Generation (CS_ILIM)
      15. 8.3.15 Hiccup Mode Operation (HICC)
      16. 8.3.16 External Fault Protection (FAULT)
      17. 8.3.17 Slope Compensation (RSC)
      18. 8.3.18 Frequency Compensation
      19. 8.3.19 Thermal Shutdown
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Switching Frequency
        2. 9.2.2.2  Output Voltage Programming Resistors
        3. 9.2.2.3  Dead Time
        4. 9.2.2.4  Leading Edge Blank Time
        5. 9.2.2.5  Soft-Start Capacitor
        6. 9.2.2.6  Transformer
        7. 9.2.2.7  Main Switching FETs
        8. 9.2.2.8  Synchronous Rectificier FETs
        9. 9.2.2.9  RCD Clamp
        10. 9.2.2.10 Output Inductor
        11. 9.2.2.11 Output Capacitance and Filter
        12. 9.2.2.12 Sense Resistor
        13. 9.2.2.13 Hiccup Capacitor
        14. 9.2.2.14 Frequency Compensation Components
        15. 9.2.2.15 Slope Compensation Resistor
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 接收文档更新通知
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 术语表
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Mechanical Data

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机械数据 (封装 | 引脚)
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订购信息

External Fault Protection (FAULT)

The FAULT pin provides the user with flexibility to implement additional protections for the converter, such as input overcurrent protection or overvoltage protection, if desired. This pin can also be utilized in the event that the user desires more stringent protections than what is offered by the controller (i.e. thermal shutdown). The user can design external logic circuitry to generate the signal necessary to drive this pin based on the protection function. If the voltage on the FAULT pin exceeds 0.6 V (typical) for a duration specified by the FAULT minimum pulse width, a fault shutdown will occur. This FAULT minimum pulse width duration, which is between 0.4 µs and 1.4 µs, is intended to prevent any spurious triggering due to short-term transients. Since any short-term transient event detected on this pin that is less than 1.4 µs in duration may not activate the FAULT pin, these events should be properly evaluated by the user in order to determine the impact to the overall system. Once the fault is detected, the SS pin is discharged and the controller outputs stop switching and stay low as long as the rising threshold is exceeded on the pin. Once the fault has subsided and the voltage of FAULT falls below the falling threshold of 0.5 V (typical), the TPS7H500x-SEP enters a delay period that is dependent on the switching frequency. This delay is appoximately equal to 15 switching frequency cycles in addition to an internal logic delay. The soft-start sequence is again initiated after the delay period has finished. Equation 15 can be used to determine the length of the fault delay.

Equation 15.

In this equation:

  • tdFLT is the fault delay duration in μs
  • fsw is the switching frequency in kHz

If the FAULT threshold is exceeded during the delay, the entire sequence is started again. Figure 8-16 shows the switching waveforms when the fault mode has been activated in the controller. Note that OUTB waveforms are only applicable for TPS7H5005-SEP and TPS7H5008-SEP.

GUID-5FE7F472-3DD6-45D3-AFB1-8ECC1C5B0460-low.png Figure 8-16 Switching Waveforms During Fault Mode