SLVSLG0 April   2026 TPS7E71

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Enable (EN)
      2. 6.3.2 Dropout Voltage
      3. 6.3.3 Undervoltage Lockout
      4. 6.3.4 Thermal Shutdown
      5. 6.3.5 Foldback Current Limit
      6. 6.3.6 Power Limit
      7. 6.3.7 Output Pulldown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Device Functional Mode Comparison
      2. 6.4.2 Normal Operation
      3. 6.4.3 Dropout Operation
      4. 6.4.4 Disabled
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Adjustable Device Feedback Resistor Selection
      2. 7.1.2 Recommended Capacitor Types
      3. 7.1.3 Input and Output Capacitor Selection
      4. 7.1.4 Reverse Current
      5. 7.1.5 Feed-Forward Capacitor
      6. 7.1.6 Dropout Voltage
      7. 7.1.7 Estimating Junction Temperature
      8. 7.1.8 Power Dissipation (PD)
      9. 7.1.9 Power Dissipation Versus Ambient Temperature
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Choose Feedback Resistors
        2. 7.2.2.2 Application Curves
      3. 7.2.3 Power Supply Recommendations
      4. 7.2.4 Layout
        1. 7.2.4.1 Layout Guidelines
        2. 7.2.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
      2. 8.1.2 Device Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

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6.3.6 Power Limit

The device has an internal over-power limit circuit that limits the power dissipated across the LDO within the internal SOA (safe operating area) limits. The SOA limits for the LDO factor in safe operation for both silicon components and bondwires used in packaging. These limits verify reliable operation of the device and prevent the device failure from overheating, breakdown, or other damaging effects.

The power dissipated (PDissip) across the LDO is defined by voltage drop across LDO (VIN - VOUT) and load current (IL) flowing through the LDO.

Equation 2. PDissip = VIN - VOUT × IOUT

The power limiting circuit monitors both the voltage drop (headroom, VIN - VOUT) across LDO and output load current (IOUT) flowing through the LDO. If PDissip crosses the defined SOA limits, the power limiting circuit limits the load current (IOUT) flowing through the LDO. The output voltage is not regulated when the device is in power limit operation. The maximum supported current (IPLIMIT) at full headroom (VIN - VOUT = 30V) and maximum supported headroom (VPHEADROOM) at full load current are captured in Electrical Characteristics.

Figure 6-4 shows a diagram of the power limiting.

TPS7E71 Power Limiting Figure 6-4 Power Limiting