SGLS155B February   2003  – November 2016 TPS768-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 Device Operation
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Power-Good Indicator
      2. 8.3.2 Regulator Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown
      2. 8.4.2 Operation With VIN Less Than 2.7 V
      3. 8.4.3 Operation With VIN Greater Than 2.7 V
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Minimum Load Requirements
        2. 9.2.2.2 FB Pin Connection (Adjustable Version Only)
        3. 9.2.2.3 Programming the TPS76801-Q1 Adjustable LDO Regulator
        4. 9.2.2.4 External Capacitor Requirements
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Power Dissipation and Junction Temperature
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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11 Layout

11.1 Layout Guidelines

Input and output capacitors should be placed as close to the device pins as possible. To improve ac performance such as PSRR, output noise, and transient response, it is recommended that the board be designed with separate ground planes for IN and OUT, with the ground planes connected only at the GND pin of the device. In addition, the ground connection for the output capacitor should be connected directly to the GND pin of the device. High-ESR capacitors may degrade PSRR performance.

11.2 Layout Example

TPS768-Q1 Layout_SGLS155.gif Figure 25. TPS768xx-Q1 Layout Example

11.3 Power Dissipation and Junction Temperature

Specified regulator operation is assured to a junction temperature of 125°C; the maximum junction temperature should be restricted to 125°C under normal operating conditions. This restriction limits the power dissipation the regulator can handle in any given application. To ensure the junction temperature is within acceptable limits, calculate the maximum allowable dissipation, PDmax, and the actual dissipation, PD, which must be less than or equal to PDmax.

The maximum power dissipation limit is determined using Equation 3:

Equation 3. TPS768-Q1 q_pdmax_SGLS155.gif

where:

TJmax = maximum allowable junction temperature

RθJA = junction-to-ambient thermal resistance for the package; that is, 32.6°C/W for the 20-pin TSSOP (PWP) with no airflow

TA = ambient temperature

The regulator dissipation is calculated using Equation 4:

Equation 4. TPS768-Q1 Q_PD_lvs211.gif

Power dissipation resulting from quiescent current is negligible. Excessive power dissipation triggers the thermal protection circuit.