SWCS032F October   2008  – July 2014 TPS65950

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Terminal Configuration and Functions
    1. 3.1 Corner Balls
    2. 3.2 Ball Characteristics
    3. 3.3 Signal Description
  4. 4Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 Handling Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 Digital I/O Electrical Characteristics
    5. 4.5 Thermal Resistance Characteristics for ZXN Package
    6. 4.6 Minimum Voltages and Associated Currents
    7. 4.7 Timing Requirements and Switching Characteristics
      1. 4.7.1 Timing Parameters
      2. 4.7.2 Target Frequencies
      3. 4.7.3 I2C Timing
      4. 4.7.4 Audio Interface: TDM/I2S Protocol
        1. 4.7.4.1 I2S Right- and Left-Justified Data Format
        2. 4.7.4.2 TDM Data Format
      5. 4.7.5 Voice/Bluetooth PCM Interfaces
      6. 4.7.6 JTAG Interfaces
  5. 5Detailed Description
    1. 5.1  Power Module
      1. 5.1.1 Power Providers
        1. 5.1.1.1  VDD1 DC-DC Regulator
          1. 5.1.1.1.1 VDD1 DC-DC Regulator Characteristics
          2. 5.1.1.1.2 External Components and Application Schematic
        2. 5.1.1.2  VDD2 DC-DC Regulator
          1. 5.1.1.2.1 VDD2 DC-DC Regulator Characteristics
          2. 5.1.1.2.2 External Components and Application Schematic
        3. 5.1.1.3  VIO DC-DC Regulator
          1. 5.1.1.3.1 VIO DC-DC Regulator Characteristics
          2. 5.1.1.3.2 External Components and Application Schematic
        4. 5.1.1.4  VDAC LDO Regulator
        5. 5.1.1.5  VPLL1 LDO Regulator
        6. 5.1.1.6  VPLL2 LDO Regulator
        7. 5.1.1.7  VMMC1 LDO Regulator
        8. 5.1.1.8  VMMC2 LDO Regulator
        9. 5.1.1.9  VSIM LDO Regulator
        10. 5.1.1.10 VAUX1 LDO Regulator
        11. 5.1.1.11 VAUX2 LDO Regulator
        12. 5.1.1.12 VAUX3 LDO Regulator
        13. 5.1.1.13 VAUX4 LDO Regulator
        14. 5.1.1.14 Internal LDOs
        15. 5.1.1.15 CP
        16. 5.1.1.16 USB LDO Short-Circuit Protection Scheme
      2. 5.1.2 Power References
      3. 5.1.3 Power Control
        1. 5.1.3.1 Backup Battery Charger
        2. 5.1.3.2 Battery Monitoring and Threshold Detection
          1. 5.1.3.2.1 Power On/Power Off and Backup Conditions
        3. 5.1.3.3 VRRTC LDO Regulator
      4. 5.1.4 Power Consumption
      5. 5.1.5 Power Management
        1. 5.1.5.1 Boot Modes
        2. 5.1.5.2 Process Modes
          1. 5.1.5.2.1 C027.0 Mode
          2. 5.1.5.2.2 C021.M Mode
        3. 5.1.5.3 Power-On Sequence
          1. 5.1.5.3.1 Timings Before Sequence_Start
          2. 5.1.5.3.2 OMAP2 Power-On Sequence
          3. 5.1.5.3.3 OMAP3 Power-On Sequence
          4. 5.1.5.3.4 Power On in Slave_C021_Generic Mode
        4. 5.1.5.4 Power-Off Sequence
          1. 5.1.5.4.1 Power-Off Sequence in Master Modes
    2. 5.2  Real-Time Clock and Embedded Power Controller
      1. 5.2.1 RTC
        1. 5.2.1.1 Backup Battery
      2. 5.2.2 EPC
    3. 5.3  Audio/Voice Module
      1. 5.3.1 Audio/Voice Downlink (RX) Module
        1. 5.3.1.1  Earphone Output
          1. 5.3.1.1.1 Earphone Output Characteristics
          2. 5.3.1.1.2 External Components and Application Schematic
        2. 5.3.1.2  8-Ω Stereo Hands-Free
          1. 5.3.1.2.1 8-Ω Stereo Hands-Free Output Characteristics
            1. 5.3.1.2.1.1 Short-Circuit Protection
          2. 5.3.1.2.2 External Components and Application Schematic
        3. 5.3.1.3  Headset
          1. 5.3.1.3.1 Headset Output Characteristics
          2. 5.3.1.3.2 External Components and Application Schematic
        4. 5.3.1.4  Headset Pop-Noise Attenuation
        5. 5.3.1.5  Predriver for External Class-D Amplifier
          1. 5.3.1.5.1 Predriver Output Characteristics
          2. 5.3.1.5.2 External Components and Application Schematic
        6. 5.3.1.6  Vibrator H-Bridge
          1. 5.3.1.6.1 Vibrator H-Bridge Output Characteristics
          2. 5.3.1.6.2 External Components and Application Schematic
        7. 5.3.1.7  Carkit Output
        8. 5.3.1.8  Digital Audio Filter Module
        9. 5.3.1.9  Digital Voice Filter Module
          1. 5.3.1.9.1 Voice Downlink Filter (Sampling Frequency at 8 kHz)
          2. 5.3.1.9.2 Voice Downlink Filter (Sampling Frequency at 16 kHz)
        10. 5.3.1.10 Boost Stage
      2. 5.3.2 Audio/Voice Uplink (TX) Module
        1. 5.3.2.1  Microphone Bias Module
          1. 5.3.2.1.1 Analog Microphone Bias Module Characteristics
          2. 5.3.2.1.2 External Components and Application Schematic
          3. 5.3.2.1.3 Digital Microphone Bias Module Characteristics
          4. 5.3.2.1.4 Silicon Microphone Characteristics
        2. 5.3.2.2  Stereo Differential Input
        3. 5.3.2.3  Headset Differential Input
        4. 5.3.2.4  FM Radio/Auxiliary Stereo Input
          1. 5.3.2.4.1 External Components
        5. 5.3.2.5  PDM Interface for Digital Microphones
        6. 5.3.2.6  Uplink Characteristics
        7. 5.3.2.7  Microphone Amplification Stage
        8. 5.3.2.8  Carkit Input
        9. 5.3.2.9  Digital Audio Filter Module
        10. 5.3.2.10 Digital Voice Filter Module
          1. 5.3.2.10.1 Voice Uplink Filter (Sampling Frequency at 8 kHz)
          2. 5.3.2.10.2 Voice Uplink Filter (Sampling Frequency at 16 kHz)
    4. 5.4  USB HS 2.0 OTG Transceiver
      1. 5.4.1 USB Features
      2. 5.4.2 USB Transceiver
        1. 5.4.2.1 MCPC Carkit Port Timing
        2. 5.4.2.2 USB-CEA Carkit Port Timing
        3. 5.4.2.3 HS USB Port Timing
        4. 5.4.2.4 PHY Electrical Characteristics
          1. 5.4.2.4.1  5-V Tolerance
          2. 5.4.2.4.2  LS/FS Single-Ended Receivers
          3. 5.4.2.4.3  LS/FS Differential Receiver
          4. 5.4.2.4.4  LS/FS Differential Transmitter
          5. 5.4.2.4.5  HS Differential Receiver
          6. 5.4.2.4.6  HS Differential Transmitter
          7. 5.4.2.4.7  CEA/MCPC/UART Driver
          8. 5.4.2.4.8  Pullup/Pulldown Resistors
          9. 5.4.2.4.9  PHY DPLL Electrical Characteristics
          10. 5.4.2.4.10 PHY Power Consumption
        5. 5.4.2.5 OTG Electrical Characteristics
          1. 5.4.2.5.1 OTG VBUS Electrical
          2. 5.4.2.5.2 OTG ID Electrical
    5. 5.5  Battery Interface
      1. 5.5.1 General Description
        1. 5.5.1.1 Battery Charger Interface Overview
        2. 5.5.1.2 Battery Backup Overview
      2. 5.5.2 Typical Application Schematics
        1. 5.5.2.1 Functional Configurations
        2. 5.5.2.2 In-Rush Current Limitation Schematic
        3. 5.5.2.3 Configuration With BCI Not Used
      3. 5.5.3 Electrical Characteristics
        1. 5.5.3.1 Main Charge
        2. 5.5.3.2 Precharge
        3. 5.5.3.3 Constant Voltage Mode
      4. 5.5.4 Charge Sequence Timing Diagram
      5. 5.5.5 CEA Charger Type
    6. 5.6  MADC
      1. 5.6.1 General Description
      2. 5.6.2 Main Electrical Characteristics
      3. 5.6.3 Channel Voltage Input Range
        1. 5.6.3.1 Sequence Conversion Time (Real-Time or Nonaborted Asynchronous)
    7. 5.7  LED Drivers
      1. 5.7.1 General Description
    8. 5.8  Keyboard
      1. 5.8.1 Keyboard Connection
    9. 5.9  Clock Specifications
      1. 5.9.1 Features
      2. 5.9.2 Input Clock Specifications
        1. 5.9.2.1 Clock Source Requirements
        2. 5.9.2.2 High-Frequency Input Clock
        3. 5.9.2.3 32-kHz Input Clock
          1. 5.9.2.3.1 External Crystal Description
          2. 5.9.2.3.2 External Clock Description
      3. 5.9.3 Output Clock Specifications
        1. 5.9.3.1 32KCLKOUT Output Clock
        2. 5.9.3.2 HFCLKOUT Output Clock
        3. 5.9.3.3 Output Clock Stabilization Time
    10. 5.10 Debouncing Time
    11. 5.11 External Components
  6. 6Device and Documentation Support
    1. 6.1 Device Support
      1. 6.1.1 Development Support
      2. 6.1.2 Device Nomenclature
    2. 6.2 Documentation Support
    3. 6.3 Community Resources
    4. 6.4 Trademarks
    5. 6.5 Electrostatic Discharge Caution
    6. 6.6 Export Control Notice
    7. 6.7 Glossary
    8. 6.8 Additional Acronyms

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • ZXN|209
散热焊盘机械数据 (封装 | 引脚)
订购信息

3 Terminal Configuration and Functions

Figure 3-1 shows the ball locations for the 209-ball plastic ball grid array (PBGA) package and is used with Table 3-1 to locate signal names and ball grid numbers.

swcs032-088.gifFigure 3-1 PBGA Bottom View

3.1 Corner Balls

The four corner balls (see the following list) are not usable for functional pins:

  • Test
  • TestV1
  • Test.RESET
  • TestV2

The eight corner adjacent balls are:

  • RFID.EN
  • UART1.TXD
  • JTAG.TDI/BERDATA
  • JTAG.CLK/BERCLK
  • PCM.VFS
  • PCM.VDX
  • PCM.VDR
  • PCM.VCK

3.2 Ball Characteristics

Table 3-1 describes the terminal characteristics and the signals multiplexed on each pin. The following list describes the column headings in Table 3-1:

  1. Ball: Ball number(s) associated with each signal(s)
  2. Pin Name: Names of all the signals that are multiplexed on each ball
  3. A/D: Analog or digital signal
  4. Type: Terminal type when a particular signal is multiplexed on the terminal
    • I = Input
    • O = Output
    • OD = Open drain
  5. Reference Level: Voltage applied to the I/O cell (see the power module and battery charger interface [BCI] chapters for values).
  6. PU/PD: Denotes the presence of an internal pullup or pulldown. Pullups and pulldowns can be enabled or disabled through software.
  7. Min = Minimum value
  8. Typ = Typical value
  9. Max = Maximum value
  10. Buffer Strength: Drive strength of the associated output buffer

Table 3-1 Ball Characteristics

Ball[1] Pin
Name[2]		 A/D
[3]		 Type[4] Reference Level
RL[5]		 PU[6] (kΩ) PD[6] (kΩ) Buffer
Strength
(mA)[10]
Min[7] Typ[8] Max[9] Min Typ Max
H4 ADCIN0 A I/O VINTANA1.OUT
J3 ADCIN1 A I/O VINTANA1.OUT
G3 ADCIN2 A I VINTANA2.OUT
P5 VCCS A I VBAT + 0.2
N5 VAC A Power VACCHARGER
P4 VBATS A I VBAT
N4 PCHGAC A I VACCHARGER
N6 PCHGUSB A I VBUS
N2 VPRECH A O VPRECH
N1 BCIAUTO A I VPRECH
P6 ICTLUSB1 A O VBUS
P1 ICTLUSB2 A O VCCS
N7 ICTLAC1 A O VACCHARGER
P2 ICTLAC2 A O VCCS
R5 VBAT A Power VBAT
P12 GPIO0/CD1 D I/O IO_1P8 75 100 202 59 100 144 8
JTAG.TDO D I/O IO_1P8 8
N12 GPIO1/CD2 D I/O IO_1P8 75 100 202 59 100 144 2
JTAG.TMS D I IO_1P8
L4 GPIO2 D I/O IO_1P8 156 220 450 59 100 144 2
Test1 D I/O IO_1P8 2
P13 GPIO15 D I/O IO_1P8 156 220 450 59 100 144 2
Test2 D I/O IO_1P8 2
M4 GPIO6 D I/O IO_1P8 75 100 202 59 100 144 2
PWM0 D O IO_1P8 4
Test3 D I/O IO_1P8 2
N14 GPIO7 D I/O IO_1P8 75 100 202 59 100 144 2
VIBRA.SYNC D I IO_1P8
PWM1 D O IO_1P8 4
Test4 D I/O IO_1P8 2
J9 START.ADC D I IO_1P8
C13 SYSEN D OD/I IO_1P8 4.7 7.35 10 2
C6 CLKEN D O IO_1P8 2
D7 CLKEN2 D O IO_1P8 2
G10 CLKREQ D I IO_1P8 60 100 146
F10 INT1 D O IO_1P8 2
F9 INT2 D O IO_1P8 2
A13 NRESPWRON D O IO_1P8 2
B13 NRESWARM D I IO_1P8 2
A11 PWRON D I VBAT
B14 NC
P7 NSLEEP1 D I IO_1P8
G9 NSLEEP2 D I IO_1P8
D13 CLK256FS(1) D O IO_1P8 2
F8 VMODE1 D I IO_1P8
K11 BOOT0 A/D I/O VBAT
J11 BOOT1 A/D I/O VBAT
A10 REGEN D OD VBAT 5.5 8 12 2
H8 MSECURE D I IO_1P8
N16 VREF A Power VREF
N15 AGND A Power GND GND
C4 NC
I2C.SR.SDA D I/O IO_1P8 2.5 3.4 12
D6 VMODE2 D I IO_1P8 2
I2C.SR.SCL D I/O IO_1P8 2.5 3.4 12
D4 I2C.CNTL.SDA D I/O IO_1P8 2.5 3.4 12
D5 I2C.CNTL.SCL D I IO_1P8 2.5 3.4 12
R1 PCM.VCK D I/O IO_1P8 2
T2 PCM.VDR D I/O IO_1P8 2
T15 PCM.VDX D I/O IO_1P8 2
R16 PCM.VFS D I/O IO_1P8 2
L3 I2S.CLK D I/O IO_1P8 2
K6 I2S.SYNC D I/O IO_1P8 2
K4 I2S.DIN D I IO_1P8 2
K3 I2S.DOUT D O IO_1P8 2
E2 MIC.MAIN.P A I MICBIAS1.OUT
F2 MIC.MAIN.M A I MICBIAS1.OUT
G2 MIC.SUB.P A I MICBIAS2.OUT
DIG.MIC.0 A I VMIC1.OUT
H2 MIC.SUB.M A I MICBIAS2.OUT
DIG.MIC.1 A I VMIC2.OUT
E3 HSMIC.P A I VINTANA2.OUT
F3 HSMIC.M A I VINTANA2.OUT
D10 VBAT.LEFT A Power VBAT
D9 VBAT.LEFT A Power VBAT
B9 IHF.LEFT.P A O VBAT
B10 IHF.LEFT.M A O VBAT
C10 GND.LEFT A Power GND GND
C9 GND.LEFT A Power GND GND
D12 VBAT.RIGHT A Power VBAT
D11 VBAT.RIGHT A Power VBAT
B11 IHF.RIGHT.P A O VBAT
B12 IHF.RIGHT.M A O VBAT
C12 GND.RIGHT A Power GND GND
C11 GND.RIGHT A Power GND GND
A6 EAR.P A O VINTANA2.OUT
A7 EAR.M A O VINTANA2.OUT
B4 HSOL A O VINTANA2.OUT
B7 PreDriv.LEFT A O VINTANA2.OUT
VMID A Power VINTANA2.OUT
B5 HSOR A O VINTANA2.OUT
B8 PreDriv.RIGHT A O VINTANA2.OUT
ADCIN7 A I VINTANA2.OUT
F1 AUXL A I VINTANA2.OUT
G1 AUXR A I VINTANA2.OUT
D1 MICBIAS1.OUT A Power VINTANA2.OUT
VMIC1.OUT A Power VINTANA2.OUT
D2 MICBIAS2.OUT A Power VINTANA2.OUT
VMIC2.OUT A Power VINTANA2.OUT
E4 VHSMIC.OUT A Power VINTANA2.OUT
D3 MICBIAS.GND Power GND GND
J4 / J6 /J7 / J8 / E5 AVSS1 A Power GND GND
R10 AVSS2 A Power GND GND
M15 AVSS3 A Power GND GND
C7 AVSS4 A Power GND GND
B1 UART1.TXD D OD External 1.8 to 3.3 V 2
D8 GPIO8 D I IO_1P8 4.7 7.4 10 5.9 7 8.3
UART1.RXD D I IO_1P8
N11 RTSO/ CLK64K.OUT/ BERCLK.OUT D OD VUSB.3P1 2
ADCIN5 A I VINTANA2.OUT
P11 CTSI/ BERDATA.OUT D OD/CMOS/I/O VUSB.3P1 4.7 7.4 10 2
ADCIN3 A I VINTANA2.OUT
N8 TXAF A I VUSB.3P1
ADCIN4 A I VINTANA2.OUT
N9 RXAF A O VUSB.3P1
ADCIN6 A I VINTANA2.OUT
L10 MANU D I VUSB.3P1 162 280 414
N10 32KCLKOUT D O IO_1P8
P16 32KXIN A I IO_1P8
P15 32KXOUT A O IO_1P8
A14 HFCLKIN A I IO_1P8
R12 HFCLKOUT D O IO_1P8
R8 VBUS A Power VBUS
T10 DP/UART3.RXD A I/O VBUS 2
T11 DN/UART3.TXD A I/O VBUS 2
R11 ID A I/O VBUS 2
L15 UCLK D I IO_1P8 16
L14 STP D I IO_1P8 75 100 202 59 100 144 16
GPIO9 D I/O IO_1P8 2
L13 DIR D O IO_1P8 75 100 202 59 100 144 16
GPIO10 D I/O IO_1P8 2
M13 NXT D O IO_1P8 75 100 202 59 100 144 16
GPIO11 D I/O IO_1P8 2
K14 DATA0 D I/O IO_1P8 16
UART4.TXD D I IO_1P8
K13 DATA1 D I/O IO_1P8 16
UART4.RXD D O IO_1P8 2
J14 DATA2 D I/O IO_1P8 16
UART4.RTSI D I IO_1P8
J13 DATA3 D I/O IO_1P8 60 100 140 60 100 140 16
UART4.CTSO D O IO_1P8 16
GPIO12 D I/O IO_1P8 75 100 202 59 100 144 16
G14 DATA4 D I/O IO_1P8 75 100 202 59 100 144 16
GPIO14 D I/O IO_1P8 2
G13 DATA5 D I/O IO_1P8 75 100 202 59 100 144 16
GPIO3 D I/O IO_1P8 2
F14 DATA6 D I/O IO_1P8 75 100 202 59 100 144 16
GPIO4 D I/O IO_1P8 2
F13 DATA7 D I/O IO_1P8 75 100 202 59 100 144 16
GPIO5 D I/O IO_1P8 2
T16 TEST.RESET A/D I VBAT 30 50 70
T1 TESTV1 A I/O VBAT
A16 TESTV2 A I/O VINTANA2.OUT
A1 TEST D I IO_1P8 60 100 146
A15 JTAG.TDI/ BERDATA D I IO_1P8
B16 JTAG.TCK/
BERCLK		 D I IO_1P8
R7 CP.IN A Power VBAT/VBUS
T7 CP.CAPP A O CP.CAPP
T6 CP.CAPM A O CP.CAPM
R6 CP.GND A Power GND GND
R9 VBAT.USB A Power VBAT
P9 VUSB.3P1 A Power VUSB.3P1
L1 VAUX12S.IN A Power VBAT
M2 VAUX1.OUT A Power VAUX1.OUT
M3 VAUX2.OUT A Power VAUX2.OUT
H15 VPLLA3R.IN A Power VBAT
K16 VRTC.OUT A Power VRTC.OUT
H14 VPLL1.OUT A Power VPLL1.OUT
J15 VSDI.CSI.OUT A Power VSDI.CSI.OUT
G16 VAUX3.OUT A Power VAUX3.OUT
B2 VAUX4.IN A Power VBAT
B3 VAUX4.OUT A Power VAUX4.OUT
C1 VMMC1.IN A Power VBAT
C2 VMMC1.OUT A Power VMMC1.OUT
A3 VMMC2.IN A Power VBAT
A4 VMMC2.OUT A Power VMMC2.OUT
K2 VSIM.OUT A Power VSIM.OUT
P8 VINTUSB1P5.
OUT		 A Power VINTUSB1P5.OUT
P10 VINTUSB1P8.
OUT		 A Power VINTUSB1P8.OUT
K1 VDAC.IN A Power VBAT
L2 VDAC.OUT A Power VDAC.OUT
K15 VINT.IN A Power VBAT
H3 VINTANA1.OUT A Power VINTANA1.OUT
J2 VINTANA2.OUT A Power VINTANA2.OUT
B6 VINTANA2.OUT A Power VINTANA2.OUT
L16 VINTDIG.OUT A Power VINTDIG.OUT
E15 VDD1.IN A Power VBAT
E14 VDD1.IN A Power VBAT
D14 VDD1.IN A Power VBAT
D16 VDD1.SW A O VBAT
D15 VDD1.SW A O VBAT
C14 VDD1.SW A O VBAT
E13 VDD1.FB A I
C16 VDD1.GND A Power GND GND
C15 VDD1.GND A Power GND GND
B15 VDD1.GND A Power GND GND
R13 VDD2.IN A Power VBAT
P14 VDD2.IN A Power VBAT
N13 VDD2.FB A I
T13 VDD2.SW A O VBAT
R14 VDD2.SW A O VBAT
T14 VDD2.GND A Power GND GND
R15 VDD2.GND A Power GND GND
P3 VIO.IN A Power VBAT
R4 VIO.IN A Power VBAT
N3 VIO.FB A I
R3 VIO.SW A O VBAT
T4 VIO.SW A O VBAT
R2 VIO.GND A Power GND GND
T3 VIO.GND A Power GND GND
M14 BKBAT A Power VBACK
C8 IO.1P8 A Power IO_1P8
H13 / H9 / H10 / H11 DGND A Power GND GND
F16 LEDGND A Power GND GND
G11 GPIO13 D I/O IO_1P8 75 100 202 59 100 144
LEDSYNC D I IO_1P8
F15 LEDA A OD VBAT
VIBRA.P A OD VBAT
G15 LEDB A OD VBAT
VIBRA.M A OD VBAT
G8 KPD.C0 D OD IO_1P8
H7 KPD.C1 D OD IO_1P8
G6 KPD.C2 D OD IO_1P8
F7 KPD.C3 D OD IO_1P8
G7 KPD.C4 D OD IO_1P8
F4 KPD.C5 D OD IO_1P8
H6 KPD.C6 D OD IO_1P8
G4 KPD.C7 D OD IO_1P8
K9 KPD.R0 D I IO_1P8 8 10 12
K8 KPD.R1 D I IO_1P8 8 10 12
L8 KPD.R2 D I IO_1P8 8 10 12
K7 KPD.R3 D I IO_1P8 8 10 12
L9 KPD.R4 D I IO_1P8 8 10 12
J10 KPD.R5 D I IO_1P8 8 10 12
K10 KPD.R6 D I IO_1P8 8 10 12
L7 KPD.R7 D I IO_1P8 8 10 12
C3 GPIO16 D I/O IO_1P8 75 100 202 59 100 144
BT.PCM.VDR D I/O IO_1P8
DIG.MIC.CLK0 D O IO_1P8
C5 GPIO17 D I/O IO_1P8 75 100 202 59 100 144
BT.PCM.VDX D I/O IO_1P8
DIG.MIC.CLK1 D O IO_1P8
A2 RFID.EN D O VMMC2.OUT
(1) To avoid reflection on this pin caused by impedance mismatch, a serial resistance (Rs) of 33 Ω must be added.

3.3 Signal Description

Table 3-2 lists the signals on the TPS65950; some signals are available on multiple pins.

Table 3-2 Signal Description

Module Signal
Name		 Description Type(1) Ball Configuration By Default After Reset Released Unused Features(2)
Signal Type(1) Internal Pull or Not
ADC ADCIN0 Battery type I/O H4 ADCIN0 I GND
ADCIN1 Battery temperature I/O J3 ADCIN1 I GND
ADCIN2 General-purpose (GP) ADC input I G3 ADCIN2 I GND
Charger VCCS Charge current sensing I P5 VCCS I Cap to GND(3)
VAC Charge device input voltage Power N5 VAC Power GND
VBATS Charge current sensing I P4 VBATS I Cap to GND(3)
PCHGAC ac precharge sense signal. Used also for EEPROM I N4 PCHGAC I GND
PCHGUSB USB precharge sense signal I N6 PCHGUSB I GND
VPRECH Precharge regulator output O N2 VPRECH O Cap to GND(3)
BCIAUTO Linear charge specific boot mode I N1 BCIAUTO I GND
ICTLUSB1 USB power device control O P6 ICTLUSB1 O Floating
ICTLUSB2 USB power device control O P1 ICTLUSB2 O Floating
ICTLAC1 ac power device control O N7 ICTLAC1 O Floating
ICTLAC2 ac power device control O P2 ICTLAC2 O Floating
VBAT Battery voltage sensing Power R5 VBAT Power VBAT
GPIOs/
JTAG		 GPIO0/CD1 GPIO0/card detection 1 I/O P12 GPIO0 I PD Floating
JTAG.TDO JTAG test data output I/O
GPIO1/CD2 GPIO1/card detection 2 I/O N12 GPIO1 I PD Floating
JTAG.TMS JTAG test mode state I
GPIO2 GPIO2 I/O L4 GPIO2 I PD Floating
Test1 Test1 pin used in test mode only I/O
GPIO15 GPIO15 I/O P13 GPIO15 I PD Floating
Test2 Test2 pin used in test mode only I/O
GPIO6 GPIO6 I/O M4 GPIO6 I PD Floating
PWM0 Pulse width driver 0 O
Test3 Test3 pin used in test mode only (controlled by JTAG) I/O
GPIO7 GPIO7 I/O N14 GPIO7 I PD Floating
VIBRA.SYNC Vibrator on-off synchronization I
PWM1 Pulse width driver O
Test4 Test4 pin used in test mode only (controlled by JTAG) I/O
START.
ADC		 START.ADC ADC conversion request I J9 START.ADC I GND
CONTROL SYSEN System enable output OD/I C13 SYSEN OD PU Floating
CLKEN Clock enable O C6 CLKEN O Floating
CLKEN2 Clock enable 2 O D7 CLKEN2 O Floating
CLKREQ Clock request I G10 CLKREQ I PD GND
INT1 Output interrupt line 1 O F10 INT1 O Floating
INT2 Output interrupt line 2 O F9 INT2 O Floating
NRESPWRON Output control the NRESPWRON of the application processor O A13 NRESPWRON O Floating
NRESWARM Input, detect user action on the reset button I B13 NRESWARM I GND
PWRON Input, detect a control command to start or stop the system I A11 PWRON I VBAT
NC Not connected B14 NC Floating
NSLEEP1 Sleep request from device 1 I P7 NSLEEP1 I GND
NSLEEP2 Sleep request from device 2 I G9 NSLEEP2 I GND
CLK256FS Control for 256 × FS CLK output O D13 CLK256FS O Floating
VMODE1 Digital voltage scaling linked with VDD1 I F8 VMODE1 I GND
BOOT0 Boot pin 0 I K11 BOOT0 I PD N/A
BOOT1 Boot pin 1 I J11 BOOT1 I PD N/A
REGEN Enable signal for external LDO OD A10 REGEN OD PU Floating
MSECURE Security and digital rights management I H8 MSECURE I N/A
VREF VREF Reference voltage Power N16 VREF Power N/A
AGND Analog ground for reference voltage Power GND N15 AGND Power GND GND
I2C SmartReflex NC Not connected C4 Signal not functional(4) Floating
I2C.SR.SDA SmartReflex I2C data I/O
VMODE2 Digital voltage scaling linked with VDD2 I D6 VMODE2 I GND
I2C.SR.SCL SmartReflex I2C data I/O
I2C I2C.CNTL.SDA GP I2C data I/O D4 I2C.CNTL.SDA I/O PU N/A
I2C.CNTL.SCL GP I2C clock I/O D5 I2C.CNTL.SCL I/O PU N/A
PCM PCM.VCK Data clock (voice port) I/O R1 PCM.VCK I/O Floating
PCM.VDR Data receive (voice port) I/O T2 PCM.VDR I/O GND
PCM.VDX Data transmit (voice port) I/O T15 PCM.VDX I/O Floating
PCM.VFS Frame synchronization (voice port) I/O R16 PCM.VFS I/O Floating
TDM I2S.CLK Clock signal (audio port) I/O L3 I2S.CLK I/O Floating
I2S.SYNC Synchronization signal (audio port) I/O K6 I2S.SYNC I/O Floating
I2S.DIN Data receive (audio port) I K4 I2S.DIN I GND
I2S.DOUT Data transmit (audio port) O K3 I2S.DOUT O Floating
ANA.MIC MIC.MAIN.P Main microphone left input (P) I E2 MIC.MAIN.P I Cap to GND
MIC.MAIN.M Main microphone left input (M) I F2 MIC.MAIN.M I Cap to GND
MIC.SUB.P Main microphone right input (P) I G2 MIC.SUB.P I Cap to GND
DIG.MIC.0 Digital microphone 0 input data I
MIC.SUB.M Main microphone right input (M) I H2 MIC.SUB.M I Cap to GND
DIG.MIC.1 Digital microphone 1 input data I
Headset microphone HSMIC.P Headset microphone input (P) I E3 HSMIC.P I Cap to GND
HSMIC.M Headset microphone input (M) I F3 HSMIC.M I Cap to GND
Hands-free VBAT.LEFT Battery voltage input Power D10 VBAT.LEFT Power VBAT
VBAT.LEFT Battery voltage input Power D9 VBAT.LEFT Power VBAT
IHF.LEFT.P Hands-free speaker output left (P) O B9 IHF.LEFT.P O Floating
IHF.LEFT.M Hands-free speaker output left (M) O B10 IHF.LEFT.M O Floating
GND.LEFT GND Power GND C10 GND.LEFT Power GND GND
GND.LEFT GND Power GND C9 GND.LEFT Power GND GND
VBAT.RIGHT Battery voltage input Power D12 VBAT.RIGHT Power VBAT
VBAT.RIGHT Battery voltage input Power D11 VBAT.RIGHT Power VBAT
GND.RIGHT GND Power GND C12 GND.RIGHT Power GND GND
GND.RIGHT GND Power GND C11 GND.RIGHT Power GND GND
IHF.RIGHT.P Hands-free speaker output right (P) O B11 IHF.RIGHT.P O Floating
IHF.RIGHT.M Hands-free speaker output right (M) O B12 IHF.RIGHT.M O Floating
Earpiece EAR.P Earpiece output differential output (P) O A6 EAR.P O Floating
EAR.M Earpiece output differential output (M) O A7 EAR.M O Floating
Headset HSOL Differential/single-ended headset left output O B4 HSOL O Floating
PreDriv.LEFT Predriver output left P for external class-D amplifier O B7 VMID Power Floating
VMID Pseudo-ground for headset output Power
HSOR Differential/single-ended headset right output (P) O B5 HSOR O Floating
PreDriv.RIGHT Predriver output right P for external class-D amplifier O B8 ADCIN7 I GND
ADCIN7 GP ADC input 7 I
AUX input AUXL Auxiliary audio input left I F1 AUXL I Cap to GND
AUXR Auxiliary audio input right I G1 AUXR I Cap to GND
VMIC BIAS MICBIAS1.
OUT		 Analog microphone bias 1 Power D1 MICBIAS1.OUT Power Floating
VMIC1.OUT Digital microphone power supply 1 Power
MICBIAS2.
OUT 		Analog microphone bias 2 Power D2 MICBIAS2.OUT Power Floating
VMIC2.OUT Digital microphone power supply 2 Power
VHSMIC.OUT Headset microphone bias Power E4 VHSMIC.OUT Power Floating
MICBIAS.GND Dedicated ground for microphones Power GND D3 MICBIAS.GND Power GND GND
AVSS1 Analog ground Power GND J4/J6/ J7/J8/E5 AVSS1 Power GND GND
AVSS2 R10 AVSS2
AVSS3 M15 AVSS3
AVSS4 C7 AVSS4
Headset UART UART1.TXD Headset UART transmit data OD B1 UART1.TXD OD PU Floating
GPIO8 GPIO8 I/O D8 GPIO8 I PD Floating
UART1.RXD Headset universal asynchronous receiver/transmitter (UART) receive data/switch detection I
MCPC RTSO/
CLK64K.OUT/ BERCLK.OUT		 Ready-to-send output/
64-kHz output clock/
Bit error ratio (BER) clock out in test mode		 OD N11 RTSO/ CLK64K.OUT/ BERCLK.OUT OD Floating
ADCIN5 GP ADC input 5 I
CTSI/
BERDATA.OUT		 Clear-to-send input/
BERDATAOUT in test mode		 OD/
CMOS/
I/O		 P11 CTSI/
BERDATA.OUT		 OD GND
ADCIN3 GP ADC input 3 I
TXAF I N8 TXAF I Cap to GND
ADCIN4 GP ADC input 4 I
RXAF O N9 RXAF O Floating
ADCIN6 GP ADC input 6 I
MANU Manufacturer pin I L10 MANU I PU Floating
Clock 32KCLKOUT Buffered output of the 32-kHz digital clock O N10 32KCLKOUT O Floating
32KXIN Input of the 32-kHz oscillator I P16 32KXIN I N/A
32KXOUT Output of the 32-kHz oscillator O P15 32KXOUT O Floating
HFCLKIN Input of the digital (or sine) HS clock I A14 HFCLKIN I N/A
HFCLKOUT HS clock output O R12 HFCLKOUT O Floating
USB PHY VBUS VBUS power rail Power R8 VBUS Power N/A
DP/ UART3.RXD USB data P/USB carkit receive data/UART3 receive data I/O T10 DP/UART3.RXD I/O N/A
DN/ UART3.TXD USB data N/USB carkit transmit data/UART3 transmit data I/O T11 DN/UART3.TXD I/O N/A
ID USB ID I/O R11 ID I/O Connected to VRUSB3V1
ULPI UCLK HS USB clock I L15 UCLK O Floating
STP HS USB stop I L14 STP I PU Floating
GPIO9 GPIO9 I/O
DIR HS USB direction O L13 DIR O Floating
GPIO10 GPIO10 I/O
NXT HS USB next O M13 NXT O Floating
GPIO11 GPIO11 I/O
DATA0 HS USB Data0 I/O K14 DATA0 O Floating
UART4.TXD UART4.TXD I
DATA1 HS USB Data1 I/O K13 DATA1 O Floating
UART4.RXD UART4.RXD O
DATA2 HS USB Data2 I/O J14 DATA2 O Floating
UART4.RTSI UART4.RTSI I
DATA3 HS USB Data3 I/O J13 DATA3 O Floating
UART4.CTSO UART4.CTSO O
GPIO12 GPIO12 I/O
DATA4 HS USB Data4 I/O G14 DATA4 O Floating
GPIO14 GPIO14 I/O
DATA5 HS USB Data5 I/O G13 DATA5 O Floating
GPIO3 GPIO3 I/O
DATA6 HS USB Data6 I/O F14 DATA6 O Floating
GPIO4 GPIO4 I/O
DATA7 HS USB Data7 I/O F13 DATA7 O Floating
GPIO5 GPIO5 I/O
Test Test.RESET Reset T2 device (except power state-machine) I T16 Test.RESET I PD GND
TestV1 Analog test I/O T1 TestV1 I/O Floating
TestV2 Analog test I/O A16 TestV2 I/O Floating
Test Selection between JTAG mode and application mode for JTAG/GPIOs (with PU or PD) I A1 Test I PD Floating
JTAG.TDI/ BERDATA JTAG.TDI/BERDATA I A15 JTAG.TDI/ BERDATA I GND
JTAG.TCK/ BERCLK JTAG.TCK/BERCLK I B16 JTAG.TCK/ BERCLK I GND
USB CP CP.IN CP input voltage Power R7 CP.IN Power VBAT
CP.CAPP CP flying capacitor P O T7 CP.CAPP O Floating
CP.CAPM CP flying capacitor M O T6 CP.CAPM O Floating
CP.GND CP ground Power GND R6 CP.GND Power GND GND
VBAT.USB VBAT.USB USB LDOs (VINTUSB1P5, VINTUSB1P8, VUSB.3P1) VBAT Power R9 VBAT.USB Power VBAT
USB.LDO VUSB.3P1 USB LDO output Power P9 VUSB.3P1 Power N/A
VAUX1 VAUX12S.IN VAUX1/VAUX2/VSIM LDO input voltage Power L1 VAUX12S.IN Power VBAT
VAUX1.OUT VAUX1 LDO output voltage Power M2 VAUX1.OUT Power Floating
VAUX2 VAUX2.OUT VAUX2 LDO output voltage Power M3 VAUX2.OUT Power Floating
VPLLA3R VPLLA3R.IN Input for VPLL1, VPLL2, VAUX3, VRTC LDOs Power H15 VPLLA3R.IN Power VBAT
VRTC VRTC.OUT VRTC internal LDO output (internal use only) Power K16 VRTC.OUT Power N/A
VPLL1 VPLL1.OUT LDO output voltage Power H14 VPLL1.OUT Power Floating
VPLL2 VSDI.CSI.OUT Output voltage of the regulator Power J15 VSDI.CSI.OUT Power Floating
VAUX3 VAUX3.OUT VAUX3 LDO output voltage Power G16 VAUX3.OUT Power Floating
VAUX4 VAUX4.IN VAUX4 LDO input voltage Power B2 VAUX4.IN Power VBAT
VAUX4.OUT VAUX4 LDO output voltage Power B3 VAUX4.OUT Power Floating
VMMC1 VMMC1.IN VMMC1 LDO input voltage Power C1 VMMC1.IN Power VBAT
VMMC1.OUT VMMC1 LDO output voltage Power C2 VMMC1.OUT Power Floating
VMMC2 VMMC2.IN VMMC2 LDO input voltage Power A3 VMMC2.IN Power VBAT
VMMC2.OUT VMMC2 LDO output voltage Power A4 VMMC2.OUT Power Floating
VSIM VSIM.OUT VSIM LDO output voltage Power K2 VSIM.OUT Power Floating
VINTUSB1
P5		 VINTUSB1P5.
OUT		 VINTUSB1P5 internal LDO output (internal use only) Power P8 VINTUSB1P5. OUT Power Floating
VINTUSB1
P8		 VINTUSB1P8.
OUT		 VINTUSB1P8 internal LDO output (internal use only) Power P10 VINTUSB1P8. OUT Power Floating
Video DAC VDAC.IN Input for VDAC, VINTANA1, and VINTANA2 LDOs Power K1 VDAC.IN Power VBAT
VDAC.OUT Output voltage of the regulator Power L2 VDAC.OUT Power Floating
VINT VINT.IN Input for VINTDIG LDO Power K15 VINT.IN Power VBAT
VINTANA1 VINTANA1.
OUT		 VINTANA1 internal LDO output (internal use only) Power H3 VINTANA1.OUT Power N/A
VINTANA2 VINTANA2.
OUT		 VINTANA2 internal LDO output (internal use only) Power J2 VINTANA2.OUT Power N/A
VINTANA2.
OUT		 VINTANA2 internal LDO output (internal use only) Power B6 VINTANA2.OUT Power N/A
VINTDIG VINTDIG.OUT VINTDIG internal LDO output (internal use only) Power L16 VINTDIG.OUT Power N/A
VDD1 VDD1.IN VDD1 DC-DC input voltage Power E15 VDD1.IN Power VBAT
VDD1.IN VDD1 DC-DC input voltage Power E14 VDD1.IN Power VBAT
VDD1.IN VDD1 DC-DC input voltage Power D14 VDD1.IN Power VBAT
VDD1.SW VDD1 DC-DC switch O D16 VDD1.SW O Floating
VDD1.SW VDD1 DC-DC switch O D15 VDD1.SW O Floating
VDD1.SW VDD1 DC-DC switch O C14 VDD1.SW O Floating
VDD1.FB VDD1 DC-DC output voltage (feedback) I E13 VDD1.FB I GND
VDD1.GND VDD1 DC-DC ground Power GND C16 VDD1.GND Power GND GND
VDD1.GND VDD1 DC-DC ground Power GND C15 VDD1.GND Power GND GND
VDD1.GND VDD1 DC-DC ground Power GND B15 VDD1.GND Power GND GND
VDD2 VDD2.IN VDD2 DC-DC input voltage Power R13 VDD2.IN Power VBAT
VDD2.IN VDD2 DC-DC input voltage Power P14 VDD2.IN Power VBAT
VDD2.FB VDD2 DC-DC output voltage (feedback) I N13 VDD2.FB I GND
VDD2.SW VDD2 DC-DC switch O T13 VDD2.SW O Floating
VDD2.SW VDD2 DC-DC switch O R14 VDD2.SW O Floating
VDD2.GND VDD2 DC-DC ground Power GND T14 VDD2.GND Power GND GND
VDD2.GND VDD2 DC-DC ground Power GND R15 VDD2.GND Power GND GND
VIO VIO.IN VIO DC-DC input voltage Power P3 VIO.IN Power VBAT
VIO.IN VIO DC-DC input voltage Power R4 VIO.IN Power VBAT
VIO.FB VIO DC-DC output voltage (feedback) I N3 VIO.FB I GND
VIO.SW VIO DC-DC switch O R3 VIO.SW O Floating
VIO.SW VIO DC-DC switch O T4 VIO.SW O Floating
VIO.GND VIO DC-DC ground Power GND R2 VIO.GND Power GND GND
VIO.GND VIO DC-DC ground Power GND T3 VIO.GND Power GND GND
Backup battery BKBAT Backup battery Power M14 BKBAT Power GND
Digital VDD IO.1P8 TPS65950 I/O input Power C8 IO.1P8 Power N/A
Digital ground DGND Digital ground Power GND H13 / H9 / H10 / H11 DGND Power GND GND
LED driver LEDGND LED driver ground Power GND F16 LEDGND Power GND GND
GPIO13 GPIO13 I/O G11 GPIO13 I PD Floating
LEDSYNC LED synchronization input I
LEDA LED leg A OD F15 Signal not functional(4) Floating
VIBRA.P H-bridge vibrator P
LEDB LED leg B OD G15 Signal not functional(4) Floating
VIBRA.M H-bridge vibrator M
Keypad KPD.C0 Keypad column 0 OD G8 KPD.C0 OD Floating
KPD.C1 Keypad column 1 OD H7 KPD.C1 OD Floating
KPD.C2 Keypad column 2 OD G6 KPD.C2 OD Floating
KPD.C3 Keypad column 3 OD F7 KPD.C3 OD Floating
KPD.C4 Keypad column 4 OD G7 KPD.C4 OD Floating
KPD.C5 Keypad column 5 OD F4 KPD.C5 OD Floating
KPD.C6 Keypad column 6 OD H6 KPD.C6 OD Floating
KPD.C7 Keypad column 7 OD G4 KPD.C7 OD Floating
KPD.R0 Keypad row 0 I K9 KPD.R0 I PU Floating
KPD.R1 Keypad row 1 I K8 KPD.R1 I PU Floating
KPD.R2 Keypad row 2 I L8 KPD.R2 I PU Floating
KPD.R3 Keypad row 3 I K7 KPD.R3 I PU Floating
KPD.R4 Keypad row 4 I L9 KPD.R4 I PU Floating
KPD.R5 Keypad row 5 I J10 KPD.R5 I PU Floating
KPD.R6 Keypad row 6 I K10 KPD.R6 I PU Floating
KPD.R7 Keypad row 7 I L7 KPD.R7 I PU Floating
Bluetooth/ digital microphone GPIO16 Bluetooth PCM receive data I/O C3 GPIO16 I PD Floating
BT.PCM.VDR GPIO16 I/O
DIG.MIC.CLK0 Digital microphone clock 0 O
GPIO17 GPIO17 I/O C5 GPIO17 I PD Floating
BT.PCM.VDX Bluetooth PCM transmit data
DIG.MIC.CLK1 Digital microphone clock 1 O
RFID RFID.EN Enable for the radio frequency identification (RFID) device O A2 RFID.EN O Floating
  1. I = Input; O = Output; OD = Open drain
  2. This column provides the connection when the associated feature is not used or not connected. When there is a pin muxing, not all functions on the muxed pin are used. But even if a function is not used, the Default Configuration column applies.
    Connection criteria:
    • Analog pins:
      • For input: GND
      • For output: Floating (except VPRECH is connected to GND)
      • For I/O if input by default: GND (except for audio features input: capacitor to ground with a 100-nF typical value capacitor)
    • Digital pins:
      • For input: GND (except keypad and STP are left floating)
      • For input and pullup: Floating
      • For output: Floating
      • For I/O and pullup: Floating

    N/A (not applicable): When the associated feature is mandatory for good functioning of the TPS65950.
  3. The VPRECH, VBATS, and VCCS signals must be connected to each other and with the CPRECH capacitor to GND (see Section 5.5.2.3, Configuration with BCI Not Used).
  4. Signal not functional indicates that no signal is presented on the pad after a release reset.