ZHCSG94L August   2013  – February 2019 TPS659038-Q1 , TPS659039-Q1

PRODUCTION DATA.  

  1. 1 器件概要
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 描述
    4. 1.4 简化方框图
  2. 2 修订历史记录
  3. 3 Device Comparison
  4. 4 Pin Configuration and Functions
    1. 4.1 Pin Functions
      1.      Pin Functions
    2. 4.2 Device Ball Mapping – 13 × 13 nFBGA, 169 Balls, 0,8-mm Pitch
    3. 4.3 Signal Descriptions
  5. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: Latch Up Rating
    6. 5.6  Electrical Characteristics: LDO Regulator
    7. 5.7  Electrical Characteristics: Dual-Phase (SMPS12 and SMPS45) and Triple-Phase (SMPS123 and SMPS457) Regulators
    8. 5.8  Electrical Characteristics: Stand-Alone Regulators (SMPS3, SMPS6, SMPS7, SMPS8, and SMPS9)
    9. 5.9  Electrical Characteristics: Reference Generator (Bandgap)
    10. 5.10 Electrical Characteristics: 16-MHz Crystal Oscillator, 32-kHz RC Oscillator, and Output Buffers
    11. 5.11 Electrical Characteristics: DC-DC Clock Sync
    12. 5.12 Electrical Characteristics: 12-Bit Sigma-Delta ADC
    13. 5.13 Electrical Characteristics: Thermal Monitoring and Shutdown
    14. 5.14 Electrical Characteristics: System Control Thresholds
    15. 5.15 Electrical Characteristics: Current Consumption
    16. 5.16 Electrical Characteristics: Digital Input Signal Parameters
    17. 5.17 Electrical Characteristics: Digital Output Signal Parameters
    18. 5.18 Electrical Characteristics: I/O Pullup and Pulldown Resistance
    19. 5.19 I2C Interface Timing Requirements
    20. 5.20 SPI Timing Requirements
    21. 5.21 Typical Characteristics
  6. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1  Power Management
      2. 6.3.2  Power Resources (Step-Down and Step-Up SMPS Regulators, LDOs)
        1. 6.3.2.1 Step-Down Regulators
          1. 6.3.2.1.1 Sync Clock Functionality
          2. 6.3.2.1.2 Output Voltage and Mode Selection
          3. 6.3.2.1.3 Current Monitoring and Short Circuit Detection
          4. 6.3.2.1.4 POWERGOOD
          5. 6.3.2.1.5 DVS-Capable Regulators
          6. 6.3.2.1.6 Non DVS-Capable Regulators
          7. 6.3.2.1.7 Step-Down Converters SMPS12 and SMPS123
            1.         a. Dual-Phase SMPS and Stand-Alone SMPS
            2.         b. Triple Phase SMPS
          8. 6.3.2.1.8 Step-Down Converter SMPS45 and SMPS457
          9. 6.3.2.1.9 Step-Down Converters SMPS3, SMPS6, SMPS7, SMPS8, and SMPS9
        2. 6.3.2.2 LDOs – Low Dropout Regulators
          1. 6.3.2.2.1 LDOVANA
          2. 6.3.2.2.2 LDOVRTC
          3. 6.3.2.2.3 LDO Bypass (LDO9)
          4. 6.3.2.2.4 LDOUSB
          5. 6.3.2.2.5 Other LDOs
      3. 6.3.3  Long-Press Key Detection
      4. 6.3.4  RTC
        1. 6.3.4.1 General Description
        2. 6.3.4.2 Time Calendar Registers
          1. 6.3.4.2.1 TC Registers Read Access
          2. 6.3.4.2.2 TC Registers Write Access
        3. 6.3.4.3 RTC Alarm
        4. 6.3.4.4 RTC Interrupts
        5. 6.3.4.5 RTC 32-kHz Oscillator Drift Compensation
      5. 6.3.5  GPADC – 12-Bit Sigma-Delta ADC
        1. 6.3.5.1 Asynchronous Conversion Request (SW)
        2. 6.3.5.2 Periodic Conversion Request (AUTO)
        3. 6.3.5.3 Calibration
      6. 6.3.6  General-Purpose I/Os (GPIO Terminals)
        1. 6.3.6.1 REGEN Output
      7. 6.3.7  Thermal Monitoring
        1. 6.3.7.1 Hot-Die Function (HD)
        2. 6.3.7.2 Thermal Shutdown (TS)
        3. 6.3.7.3 Temperature Monitoring With External NTC Resistor or Diode
      8. 6.3.8  Interrupts
      9. 6.3.9  Control Interfaces
        1. 6.3.9.1 I2C Interfaces
          1. 6.3.9.1.1 I2C Implementation
          2. 6.3.9.1.2 F/S Mode Protocol
          3. 6.3.9.1.3 HS Mode Protocol
        2. 6.3.9.2 SPI Interface
          1. 6.3.9.2.1 SPI Modes
          2. 6.3.9.2.2 SPI Protocol
      10. 6.3.10 Device Identification
    4. 6.4 Device Functional Modes
      1. 6.4.1  Embedded Power Controller
      2. 6.4.2  State Transition Requests
        1. 6.4.2.1 ON Requests
        2. 6.4.2.2 OFF Requests
        3. 6.4.2.3 SLEEP and WAKE Requests
      3. 6.4.3  Power Sequences
      4. 6.4.4  Start Up Timing and RESET_OUT Generation
      5. 6.4.5  Power On Acknowledge
        1. 6.4.5.1 POWERHOLD Mode
        2. 6.4.5.2 AUTODEVON Mode
      6. 6.4.6  BOOT Configuration
        1. 6.4.6.1 Boot Terminal Selection
      7. 6.4.7  Reset Levels
      8. 6.4.8  Warm Reset
      9. 6.4.9  RESET_IN
      10. 6.4.10 Watchdog Timer (WDT)
      11. 6.4.11 System Voltage Monitoring
        1. 6.4.11.1 Generating a POR
  7. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1  Recommended External Components
        2. 7.2.2.2  SMPS Input Capacitors
        3. 7.2.2.3  SMPS Output Capacitors
        4. 7.2.2.4  SMPS Inductors
        5. 7.2.2.5  LDO Input Capacitors
        6. 7.2.2.6  LDO Output Capacitors
        7. 7.2.2.7  VCC1
          1. 7.2.2.7.1 Meeting the Power Down Sequence
          2. 7.2.2.7.2 Maintaining Sufficient Input Voltage
        8. 7.2.2.8  VIO_IN
        9. 7.2.2.9  16-MHz Crystal
        10. 7.2.2.10 GPADC
      3. 7.2.3 Application Curves
  8. 8 Power Supply Recommendations
  9. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  10. 10器件和文档支持
    1. 10.1 器件支持
      1. 10.1.1 第三方产品免责声明
      2. 10.1.2 器件命名规则
    2. 10.2 文档支持
      1. 10.2.1 相关文档
    3. 10.3 相关链接
    4. 10.4 接收文档更新通知
    5. 10.5 社区资源
    6. 10.6 商标
    7. 10.7 静电放电警告
    8. 10.8 Glossary
  11. 11机械、封装和可订购信息
    1. 11.1 封装材料信息

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • ZWS|169
散热焊盘机械数据 (封装 | 引脚)
订购信息

4.3 Signal Descriptions

Table 4-1 Summary of Digital Signals and Some Dedicated Analog Signals

SIGNAL NAME POWER DOMAIN / TOLERANCE LEVEL I/O INPUT PU/PD (2) OTP PU/PD SELECTION OUTPUT TYPE SELECTION ACTIVE HI/LO OTP POLARITY SELECTION
PWRON VSYS (VCC1) Input PU fixed N/A (fixed) N/A (input) Low No
RPWRON VSYS (VCC1) Input PU fixed N/A (fixed) N/A (input) Low No
PWRDOWN VRTC, fail-safe
(5.25-V tolerance)		 Input PPD(1) (Optional Ext.PU) Yes N/A (input) Low or high(1) Yes
POWERGOOD VRTC Output N/A (output) N/A (output) Open-drain Low or high(1) Yes
BOOT0 VRTC Input No No N/A (input) Boot conf. No
BOOT1 VRTC Tri-level input PPU/PPD(1) No N/A (input) Boot conf. No
GPIO_0 VRTC, fail-safe
(5.25-V tolerance)		 Input(1)/output PPD(1) Yes Open-drain Low or high No
GPIO_1
(primary function)		 VSYS Input(1)/output PPU/PPD(1) Yes Push-pull(1) or open- drain Low or high No
GPIO_1
secondary function:
VBUSDET		 Output N/A (output) N/A (output) Push-pull(1) or open- drain High
GPIO_2
(primary function)		 VSYS Input(1)/output PPU/PPD(1) Yes Push-pull(1) or open- drain Low or high No
GPIO_2
secondary function:
REGEN2		 Output N/A (output) N/A (output) Push-pull(1) or open- drain High
GPIO_3 VRTC, fail-safe
(5.25-V tolerance)		 Input(1)/output PPD(1) Yes Open-drain Low or high(1) Yes
GPIO_4
(primary function)		 VIO (VIO_IN) Input(1)/output PPU/PPD(1) No Push-pull Low or high No
GPIO_4
secondary function:
SYSEN1		 Output N/A (output) N/A (output) High
GPIO_5
(primary function) 		VRTC Input(1)/output PPU/PPD(1) No Push-pull(1) or open- drain Low or high No
GPIO_5
secondary function:
CLK32KGO1V8 or SYNCCLKOUT		 Output N/A (output) N/A (output) Push-pull Toggling No
GPIO_6
(primary function)		 VIO (VIO_IN) Input(1)/output PPU/PPD(1) No Push-pull Low or high No
GPIO_6
secondary function:
SYSEN2 		Output N/A (output) N/A (output) High
GPIO_7
(primary function)		 VRTC, fail-safe
(5.25-V tolerance)		 Input(1)/output PPD(1) Yes Open-drain Low or high No
GPIO_7
secondary function:
POWERHOLD 		Input PD fixed No N/A (input) High
NSLEEP VRTC Input PPU(1)/PPD No N/A (input) Low(1) or high No but software possible
ENABLE1 VIO (VIO_IN) Input PPU/PPD(1) No N/A (input) Low or high(1) No but software possible
REGEN1 VSYS (VCC1) Output N/A (output) N/A (output) Push-pull or open- drain (OTP selection) High No
RESET_IN VRTC, fail-safe
(5.25-V tolerance)		 Input PPD(1) Yes N/A (input) Low(1) or high Yes
RESET_OUT VIO (VIO_IN) Output N/A (output) N/A (output) Push-pull Low No
NRESWARM VRTC Input PPU(1) No N/A (input) Low No
INT VIO (VIO_IN) Output N/A (output) N/A (output) Push-pull(1) or open- drain Low(1) or high No but software possible
CLK32KGO VIO (VIO_IN) Output N/A (output) N/A (output) Push-pull Toggling No
I2C1_SDA_SDI VIO (VIO_IN) Input/output No No Open-drain High (I2C) Yes (I2C/SPI)
I2C1_SCL_SCK VIO (VIO_IN) Input No No N/A (input) High (I2C) Yes (I2C/SPI)
I2C2_SCL_SCE VIO (VIO_IN) Input No No N/A (input) High (I2C) Yes (I2C/SPI)
I2C2_SDA_SD0 VIO (VIO_IN) Input/output No No Open-drain (I2C) or Push-pull (SPI) High (I2C) Yes (I2C/SPI)
GPADC_IN0 VRTC Input No No N/A (analog) Analog No
GPADC_IN1 VANA Input No No N/A (analog) Analog No
GPADC_IN2 VANA Input No No N/A (analog) Analog No
GPADC_VREF VANA Output No No N/A (analog) Analog No
OSC16MIN VRTC Input No No N/A (analog) Analog No
OSC16MOUT VRTC Output No No N/A (analog) Analog No
VCC_SENSE2 VSYS (VCC1) Input No No N/A (analog) Analog No
VCC_SENSE VSYS (VCC1) Input No No N/A (analog) Analog No
(1) Default option.
(2) Pullup and pulldown resistors: PU = Pullup, PD = Pulldown, PPU = Software-programmable pullup, PPD = Software-programmable pulldown.