8.3.1 DC-DC Converters

The TPS65708 step-down converters operate with typically 2.25-MHz fixed-frequency pulse width modulation (PWM) at moderate to heavy load currents. With MODE pin set to low, at light load currents the converter can automatically enter Power Save Mode and operates then in PFM mode.

During PWM operation, the converter uses a unique fast response voltage mode control scheme with input voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output capacitors. At the beginning of each clock cycle initiated by the clock signal, the high-side MOSFET switch is turned on. The current flows now from the input capacitor through the high-side MOSFET switch through the inductor to the output capacitor and load. During this phase, the current ramps up until the PWM comparator trips and the control logic will turn off the switch. The current limit comparator will also turn off the switch in case the current limit of the high-side MOSFET switch is exceeded. After an off time preventing shoot through current, the low-side MOSFET rectifier is turned on and the inductor current will ramp down. The current flows now from the inductor to the output capacitor and to the load, and returns back to the inductor through the low-side MOSFET rectifier.

The next cycle is initiated by the clock signal again turning off the low-side MOSFET rectifier and turning on the on the high-side MOSFET switch. A 180° phase shift between DCDC1 and DCDC2 decreases the input RMS current and synchronizes the operation of the two DC-DC converters. The FB pin must directly be connected to the output voltage of the DC-DC converter and no external resistor network must be connected. As the Feedback input serves as the power input to the LOD, the external connection should be as short and as thick as possible to keep the voltage drop as small as possible.

8.3.2 Power Save Mode

The Power Save Mode is enabled with Mode Pin set to low. If the load current decreases, the converter will enter Power Save Mode operation automatically. During Power Save Mode the converter skips switching and operates with reduced frequency in PFM mode with a minimum quiescent current to maintain high efficiency. The converter positions the output voltage typically +1% above the nominal output voltage. This voltage positioning feature minimizes voltage drops caused by a sudden load step. The transition from PWM mode to PFM mode occurs once the inductor current in the low-side MOSFET switch becomes zero, which indicates discontinuous conduction mode. During the Power Save Mode the output voltage is monitored with a PFM comparator. As the output voltage falls below the PFM comparator threshold of VOUT nominal +1%, the device starts a PFM current pulse. The high-side MOSFET switch will turn on, and the inductor current ramps up. After the On-time expires, the switch is turned off and the low-side MOSFET switch is turned on until the inductor current becomes zero. The converter effectively delivers a current to the output capacitor and the load. If the load is below the delivered current, the output voltage will rise. If the output voltage is equal or higher than the PFM comparator threshold, the device stops switching and enters a sleep mode with typical 25-µA current consumption.

If the output voltage is still below the PFM comparator threshold, a sequence of further PFM current pulses are generated until the PFM comparator threshold is reached. The converter starts switching again once the output voltage drops below the PFM comparator threshold. With a fast single threshold comparator, the output voltage ripple during PFM mode operation can be kept small. The PFM Pulse is time controlled, which allows to modify the charge transferred to the output capacitor by the value of the inductor. The resulting PFM output voltage ripple and PFM frequency depend in first order on the size of the output capacitor and the inductor value. Increasing output capacitor values and inductor values will minimize the output ripple. The PFM frequency decreases with smaller inductor values and increases with larger values. The PFM mode is left and PWM mode is entered in case the output current can not longer be supported in PFM mode. The Power Save Mode can be disabled by setting Mode pin to high. The converter will then operate in fixed-frequency PWM mode.

8.3.3 Dynamic Voltage Positioning

This feature reduces the voltage undershoots and overshoots at load steps from light to heavy load and heavy to light. The feature is active in Power Save Mode and regulates the output voltage 1% higher than the nominal value. This provides more headroom for both the voltage drop at a load step, and the voltage increase at a load throw-off.

Figure 12. Dynamic Voltage Positioning

8.3.4 Soft Start

The step-down converter in TPS65708 has an internal soft-start circuit that controls the ramp up of the output voltage. The output voltage ramps up from 5% to 95% of its nominal value within typical 250 µs. This limits the inrush current in the converter during ramp up and prevents possible input voltage drops when a battery or high impedance power source is used.

Figure 13. Soft Start

8.3.5 100% Duty Cycle Low Dropout Operation

The device starts to enter 100% duty cycle mode once the input voltage comes close to the nominal output voltage. In order to maintain the output voltage, the high-side MOSFET switch is turned on 100% for one or more cycles. With further decreasing VIN the high-side MOSFET switch is turned on completely. In this case, the converter offers a low input-to-output voltage difference. This is particularly useful in battery-powered applications to achieve longest operation time by taking full advantage of the whole battery voltage range. The minimum input voltage to maintain regulation depends on the load current and output voltage, and can be calculated as:

8.3.6 180° Out-of-Phase Operation

In PWM Mode, the converters operate with a 180° turn-on phase shift of the PMOS (high-side) transistors. This prevents the high-side switches of both converters from being turned on simultaneously, and therefore smooths the input current. This feature reduces the surge current drawn from the supply.

8.3.7 Undervoltage Lockout and Enable for DCDC1, DCDC2, LDO1, and LDO2

The undervoltage lockout circuit prevents the device from malfunctioning at low input voltages and from excessive discharge of the battery. The circuit disables the DC-DC converters and LDOs at too low input voltages.

As TPS65708 does not have enable pins for the DC-DC converters and LDOs, the internal undervoltage lockout not only serves as a protection circuit but also as an enable circuitry. The supply voltage to TPS65708 is internally sensed at pin V_CC. When the voltage at V_CC exceeds 3.6 V, the internal enable signals to the DC-DC converter and LDOs are set HIGH to start-up the outputs in the pre-defined sequence. When the supply voltage drops below 3.6 V, the DC-DC converters and LDOs are disabled again and the discharge circuitry is enabled to make sure the voltage at the output capacitor ramps down quickly. Disabling the DC-DC converter or LDO, forces the device into shutdown, with a shutdown quiescent current as defined in the electrical characteristics. In this mode, the power FETs are turned off and the entire internal control circuitry is switched off.

8.3.8 Output Voltage Discharge

The DC-DC converters and LDOs contain an output capacitor discharge feature which makes sure that the capacitor is discharged when the supply voltage drops below the undervoltage lockout threshold. The discharge has a built in delay function, so the output discharge is active for a couple of 100 ms after the V_CC voltage dropped below its undervoltage lockout threshold. This will make sure that the capacitor is discharged even the supply voltage dropped below 2.1 V. The discharge function is also enabled when voltage is applied at V_CC starting at about 2.1 V until the voltage exceeded the undervoltage lockout threshold that enables the power-up sequencing.

8.3.9 Power-Up Sequencing

Three different power-up sequencing options are available. The options are factory set and can not be changed by the user. Contact TI if an option different from the default is needed.

• DCDC1, DCDC2, LDO1, and LDO2 are turning on at the same time.
• DCDC1 first, when power good, LDO1 is enabled, when power good, DCDC2 is enabled when power good, LDO2 is enabled
• DCDC2 first, when power good, LDO2 is enabled, when power good, DCDC1 is enabled when power good, LDO1 is enabled

The TPS65708 is set to option 2 such that DCDC1 starts first followed by LDO1, DCDC2, and LDO2.

8.3.10 Short-Circuit Protection

All outputs are short-circuit protected with a maximum output current as defined in Electrical Characteristics.

8.3.11 Thermal Shutdown

As soon as the junction temperature, T_J, exceeds typically 150°C for the DC-DC converters or LDOs, the device goes into thermal shutdown. In this case, the low-side and high-side MOSFETs for the DC-DC converters as well as the LDOs are turned off. The device continues its operation and powers up the DC-DC converters and LDOs with the pre-defined sequencing when the junction temperature falls below the thermal shutdown hysteresis again. During thermal shutdown also the LED driver is disabled.

8.3.12 LDOs

The low dropout voltage regulators are designed to operate well with low value ceramic input and output capacitors. They operate with input voltages down to 1.7 V. Both LDOs offer a maximum dropout voltage of 300 mV at rated output current. The LDOs support a current limit feature.

8.3.13 LED Driver

The TPS65708 contains a LED driver for a current of up to 30 mA. ISINK is an open drain current sink that regulates a current in an LED. The anode of the LED needs to be tied to a positive supply voltage; for example, V_CC or the output voltage of one of the DC-DC converters in TPS65708, depending on the forward voltage of the LED. The cathode of the LED is connected to ISINK which sets a constant current to GND. ISINK is regulated internally based on the default current set internally. In addition, the LED current can be PWM dimmed by a signal applied to pin PWM. If pin PWM is pulled LOW, the LED driver is disabled and its output ISINK is high resistive. If PWM is HIGH, the current sink regulates to the current defined by EEPROM (TI factory set in two ranges. 7.5 mA to 15 mA with 0.5-mA resolution and 15 mA to 30 mA in 1-mA resolution). The maximum PWM frequency is 50 kHz with a duty cycle range of 5% to 100%. The TPS65708 is set to 7.5 mA as a default. Contact TI about different default settings.