ZHCSCV2C june 2014 – may 2023 TPS65263
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| INPUT SUPPLY VOLTAGE | ||||||
| VIN | Input voltage range | 4.5 | 18 | V | ||
| UVLO | VIN undervoltage lockout | VIN rising | 4 | 4.25 | 4.5 | V |
| VIN falling | 3.5 | 3.75 | 4 | V | ||
| Hysteresis | 500 | mV | ||||
| IDDSDN | Shutdown supply current | EN1 = EN2 = EN3 = 0 V | 8 | µA | ||
| IDDQ_NSW | Input quiescent current without buck1/2/3 switching | EN1 = EN2 = EN3 = 5 V, FB1 = FB2 = FB3 = 0.8 V | 740 | µA | ||
| IDDQ_NSW1 | EN1 = 5 V, EN2 = EN3 = 0 V, FB1 = 0.8 V | 360 | µA | |||
| IDDQ_NSW2 | EN2 = 5 V, EN1 = EN3 = 0 V, FB2 = 0.8 V | 380 | µA | |||
| IDDQ_NSW3 | EN3 = 5 V, EN1 = EN2 = 0 V, FB3 = 0.8 V | 380 | µA | |||
| V7V | V7V LDO output voltage | V7V load current = 0 A | 6 | 6.3 | 6.6 | V |
| IOCP_V7V | V7V LDO current limit | 185 | mA | |||
| FEEDBACK VOLTAGE REFERENCE | ||||||
| VFB | Feedback voltage | VCOMP = 1.2 V, TJ = 25°C | 0.595 | 0.6 | 0.605 | V |
| VCOMP = 1.2 V, TJ = –40°C to 125°C | 0.594 | 0.6 | 0.606 | V | ||
| VLINEREG_BUCK | Line regulation-DC(1) | IOUT1 = 1.5 A, IOUT2 = 1 A, IOUT3 = 1 A, 5 V < PVINx < 18 V | 0.002 | %/V | ||
| VLOADREG_BUCK | Load regulation-DC(1) | IOUTx = (10-100%) × IOUTx_max | 0.02 | %/A | ||
| BUCK1, BUCK2, BUCK3 | ||||||
| VENXH | EN1/2/3 high level input voltage | 1.2 | 1.26 | V | ||
| VENXL | EN1/2/3 low level input voltage | 1.1 | 1.15 | V | ||
| IENX1 | EN1/2/3 pullup current | ENx = 1 V | 3.8 | µA | ||
| IENX2 | EN1/2/3 pullup current | ENx = 1.5 V | 6.8 | µA | ||
| IENhys | Hysteresis current | 3 | µA | |||
| ISSX | Soft start charging current | 4.3 | 5 | 6 | µA | |
| TON_MIN | Minimum on time | 80 | 100 | ns | ||
| Gm_EA | Error amplifier trans-conductance | –2 µA < ICOMPX < 2 µA | 300 | µS | ||
| Gm_PS1/2/3 | COMP1/2/3 voltage to inductor current Gm(1) | ILX = 0.5 A | 7.4 | A/V | ||
| ILIMIT1 | Buck1 peak inductor current limit | 4.5 | 5.5 | 6.5 | A | |
| ILIMITSOURCE1 | Buck1 low side source current limit | 4.4 | A | |||
| ILIMITSINK1 | Buck1 low side sink current limit | 1.3 | ||||
| ILIMIT2/3 | buck2/3 peak inductor current limit | 2.6 | 3.3 | 4 | A | |
| ILIMITSOURCE2/3 | Buck2/3 low side source current limit | 2.5 | ||||
| ILIMITSINK2/3 | Buck2/3 low side sink current limit | 1 | A | |||
| Rdson_HS1 | Buck1 high-side switch resistance | VIN = 12 V | 105 | mΩ | ||
| Rdson_LS1 | Buck1 low-side switch resistance | VIN = 12 V | 65 | mΩ | ||
| Rdson_HS2 | Buck2 high-side switch resistance | VIN = 12 V | 140 | mΩ | ||
| Rdson_LS2 | Buck2 low-side switch resistance | VIN = 12 V | 90 | mΩ | ||
| Rdson_HS3 | Buck3 high-side switch resistance | VIN = 12 V | 140 | mΩ | ||
| Rdson_LS3 | Buck3 low-side switch resistance | VIN = 12 V | 90 | mΩ | ||
| HICCUP TIMING | ||||||
| THiccup_wait | Over current wait time(1) | 0.5 | ms | |||
| THiccup_re | Hiccup time before restart(1) | 14 | ms | |||
| OSCILLATOR | ||||||
| FSW | Switching frequency | 550 | 600 | 650 | kHz | |
| THERMAL PROTECTION | ||||||
| TTRIP_OTP | Thermal protection trip point(1) | Temperature rising | 160 | °C | ||
| THYST_OTP | Thermal protection Hysteresis(1) | Hysteresis | 20 | °C | ||
| I2C INTERFACE | ||||||
| Addr | Address(2) | 0x60H | ||||
| VIH SDA,SCL | Input high voltage | 2 | V | |||
| VIL SDA,SCL | Input low voltage | 0.4 | V | |||
| II | Input current | SDA, SCL, VI = 0.4 to 4.5 V | –10 | 10 | µA | |
| VOL SDA | SDA output low voltage | SDA open drain, IOL = 4 mA | 0.4 | V | ||
| ƒ(SCL) | Maximum SCL clock frequency(2) | 400 | kHz | |||
| tBUF | Bus free time between a STOP and START condition(2) | 1.3 | µs | |||
| tHD_STA | Hold time (repeated) START condition(2) | 0.6 | µs | |||
| tSU_STO | Setup time for STOP condition(2) | 0.6 | µs | |||
| tLOW | LOW Period of the SCL Clock(2) | 1.3 | µs | |||
| tHIGH | HIGH period of the SCL clock(2) | 0.6 | µs | |||
| tSU_STA | Setup time for a repeated START condition(2) | 0.6 | µs | |||
| tSU_DAT | Data setup time(2) | 0.1 | µs | |||
| tHD_DAT | Data hold time(2) | 0 | 0.9 | µs | ||
| tRCL | Rise time of SCL signal(2) | Capacitance of one bus line (pF) | 20 + 0.1CB | 300 | ns | |
| tRCL1 | Rise time of SCL signal after a repeated START condition and after an acknowledge BIT(2) | Capacitance of one bus line (pF) | 20 + 0.1CB | 300 | ns | |
| tFCL | Fall time of SCL signal(2) | Capacitance of one bus line (pF) | 20 + 0.1CB | 300 | ns | |
| tRDA | Rise time of SDA signal(2) | Capacitance of one bus line (pF) | 20 + 0.1CB | 300 | ns | |
| tFDA | Fall time of SDA signal(2) | Capacitance of one bus line (pF) | 20 + 0.1CB | 300 | ns | |
| CB | Capacitance of bus line(SCL and SDA)(2) | 400 | pF | |||