ZHCSNM6A May   2021  – August 2021 TPS6521855

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
    1.     4
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Wake-Up and Power-Up and Power-Down Sequencing
        1. 7.3.1.1  Power-Up Sequencing
        2. 7.3.1.2  Power-Down Sequencing
        3. 7.3.1.3  Strobe 1 and Strobe 2
        4. 7.3.1.4  Supply Voltage Supervisor and Power-Good (PGOOD)
        5. 7.3.1.5  Internal LDO (INT_LDO)
        6. 7.3.1.6  Current Limited Load Switches
          1. 7.3.1.6.1 Load Switch 1 (LS1)
          2. 7.3.1.6.2 Load Switch 2 (LS2)
          3. 7.3.1.6.3 Load Switch 3 (LS3)
        7. 7.3.1.7  LDO1
        8. 7.3.1.8  UVLO
        9. 7.3.1.9  Power-Fail Comparator
        10. 7.3.1.10 DCDC3 and DCDC4 Power-Up Default Selection
        11. 7.3.1.11 I/O Configuration
          1. 7.3.1.11.1 Using GPIO3 as Reset Signal to DCDC1 and DCDC2
        12. 7.3.1.12 Push Button Input (PB)
          1. 7.3.1.12.1 Signaling PB-Low Event on the nWAKEUP Pin
          2. 7.3.1.12.2 Push Button Reset
        13. 7.3.1.13 AC_DET Input (AC_DET)
        14. 7.3.1.14 Interrupt Pin (INT)
        15. 7.3.1.15 I2C Bus Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
      2. 7.4.2 OFF
      3. 7.4.3 ACTIVE
      4. 7.4.4 SUSPEND
      5. 7.4.5 RESET
    5. 7.5 Register Maps
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Applications Without Backup Battery
      2. 8.1.2 Applications Without Battery Backup Supplies
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Filter Design
        2. 8.2.2.2 Inductor Selection for Buck Converters
        3. 8.2.2.3 Output Capacitor Selection
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 静电放电警告
    6. 11.6 术语表
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information
      2. 12.1.2 Tape and Reel Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Power-Up Sequencing

When the power-up sequence initiates, STROBE 1 occurs, and any rail assigned to this strobe is enabled. After a delay time of DLY1, STROBE 2 occurs and the rail assigned to this strobe is powered up. The sequence continues until all strobes occur and all DLYx times execute. Strobe assignments and delay times are defined in the SEQx registers, and are changed under I2C control. The power-up sequence executes if one of the following events occurs:

  • From the OFF state:
    • The push-button (PB) is pressed (falling edge on PB) or
    • The AC_DET pin is pulled low (falling edge) or
    • The PWR_EN is asserted (driven to high-level) or
    • The main power is connected (IN_BIAS) and AC_DET is grounded and
    • The device is not in undervoltage lockout (UVLO) or overtemperature shutdown (OTS).
  • From the PRE_OFF state:
    • The PB is pressed (falling edge on PB) or
    • The AC_DET pin is pulled low (falling edge) or
    • The PWR_EN is asserted (driven to high-level) and
    • The device is not in UVLO or OTS.
  • From the SUSPEND state:
    • The PB is pressed (falling edge on PB) or
    • The AC_DET pin is pulled low (falling edge) or
    • The PWR_EN pin is pulled high (level sensitive) and
    • The device is not in UVLO or OTS.

When a power-up event is detected, the device enters a WAIT_PWR_EN state and triggers the power-up sequence. The device remains in WAIT_PWR_EN as long as the PWR_EN and either the PB or AC_DET pin are held low. If both, the PB and AC_DET return to logic-high state and the PWR_EN pin has not been asserted within 20 s of entering WAIT_PWR_EN state, the power-down sequence is triggered and the device returns to OFF state. Once PWR_EN is asserted, the device advances to ACTIVE state, which is functionally equivalent to WAIT_PWR_EN. However, the AC_DET pin is ignored and power-down is controlled by the PWR_EN pin only.

Rails not assigned to a strobe (SEQ = 0000b) are not affected by power-up and power-down sequencing and remain in their current ON or OFF state regardless of the sequencer. A rail can be enabled and disabled at any time by setting the corresponding enable bit in the ENABLEx register, with the exception that the ENABLEx register cannot be accessed while the sequencer is active. Enable bits always reflect the current enable state of the rail. For example, the sequencer sets and resets the enable bits for the rails under its control.

Note:

The power-up sequence is defined by strobes and delay times, and can be triggered by the PB, AC_DET (not shown, same as PB), or PWR_EN pin.

GUID-EE2556F4-0A6D-40E7-85CF-2BB11AA94C5B-low.gif
Push-button deglitch time is not shown.
Figure 7-1 Power-Up Sequences from OFF or SUSPEND State; PB is Power-Up Event
GUID-29927943-0D86-46C3-860C-6D4B0EF14A9D-low.gif Figure 7-2 Power-Up Sequences from SUSPEND State; PWR_EN is Power-Up Event
GUID-DFCD0D72-960F-411A-A5FF-82B122117250-low.gif Figure 7-3 Power-Up Sequences from RECOVERY State