ZHCSBL3C June   2013  – May 2017 TPS65150-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Boost Converter
        1. 7.3.1.1 Setting the Boost Converter Output Voltage
        2. 7.3.1.2 Boost Converter Rectifier Diode
        3. 7.3.1.3 Choosing the Boost Converter Output Capacitance
        4. 7.3.1.4 Compensation
        5. 7.3.1.5 Soft Start
        6. 7.3.1.6 Gate Drive Signal
      2. 7.3.2 Negative Charge Pump
        1. 7.3.2.1 Negative Charge Pump Output Voltage
        2. 7.3.2.2 Negative Charge Pump Flying Capacitance
        3. 7.3.2.3 Negative Charge Pump Output Capacitance
        4. 7.3.2.4 Negative Charge Pump Diodes
      3. 7.3.3 Positive Charge Pump
        1. 7.3.3.1 Positive Charge Pump Output Voltage
        2. 7.3.3.2 Positive Charge Pump Flying Capacitance
        3. 7.3.3.3 Positive Charge Pump Output Capacitance
        4. 7.3.3.4 Positive Charge Pump Diodes
      4. 7.3.4 Power-On Sequencing, DLY1, DLY2
      5. 7.3.5 Gate Voltage Shaping
      6. 7.3.6 VCOM Buffer
      7. 7.3.7 Protection
        1. 7.3.7.1 Boost Converter Overvoltage Protection
        2. 7.3.7.2 Adjustable Fault Delay
        3. 7.3.7.3 Thermal Shutdown
        4. 7.3.7.4 Undervoltage Lockout
    4. 7.4 Device Functional Modes
      1. 7.4.1 VI > VIT+
      2. 7.4.2 VI < VIT-
      3. 7.4.3 Fault Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Boost Converter Design Procedure
          1. 8.2.2.1.1 Inductor Selection
        2. 8.2.2.2  Rectifier Diode Selection
        3. 8.2.2.3  Setting the Output Voltage
        4. 8.2.2.4  Output Capacitor Selection
        5. 8.2.2.5  Input Capacitor Selection
        6. 8.2.2.6  Compensation
        7. 8.2.2.7  Negative Charge Pump
          1. 8.2.2.7.1 Choosing the Output Capacitance
          2. 8.2.2.7.2 Choosing the Flying Capacitance
          3. 8.2.2.7.3 Choosing the Feedback Resistors
          4. 8.2.2.7.4 Choosing the Diodes
        8. 8.2.2.8  Positive Charge Pump
          1. 8.2.2.8.1 Choosing the Flying Capacitance
          2. 8.2.2.8.2 Choosing the Output Capacitance
          3. 8.2.2.8.3 Choosing the Feedback Resistors
          4. 8.2.2.8.4 Choosing the Diodes
        9. 8.2.2.9  Gate Voltage Shaping
        10. 8.2.2.10 Power-On Sequencing
        11. 8.2.2.11 Fault Delay
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 接收文档更新通知
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

10 Layout

10.1 Layout Guidelines

The PCB layout is an important step in the power supply design. An incorrect layout could cause converter instability, load regulation problems, noise, and EMI issues. Especially with a switching DC-DC converter at high load currents, too-thin PCB traces can cause significant voltage spikes. Good grounding is also important. If possible, TI recommends using a common ground plane to minimize ground shifts between analog ground (GND) and power ground (PGND). Additionally, the following PCB design layout guidelines are recommended for the TPS65150-Q1 device:

  1. Boost converter output capacitor, input capacitor and Power ground (PGND) must form a star ground or must be directly connected together on a common power ground plane.
  2. Place the input capacitor directly from the input pin (VIN) to ground.
  3. Use a bold PCB trace to connect SUP to the output Vs.
  4. Place a small bypass capacitor from the SUP pin to ground.
  5. Use short traces for the charge-pump drive pins (DRVN, DRVP) of VGH and VGL because these traces carry switching currents.
  6. Place the charge pump flying capacitors as close as possible to the DRVP and DRVN pin, avoiding a high voltage spikes at these pins.
  7. Place the Schottky diodes as close as possible to the device and to the flying capacitors connected to DRVP and DRVN.
  8. Carefully route the charge pump traces to avoid interference with other circuits because they carry high voltage switching currents .
  9. Place the output capacitor of the VCOM buffer as close as possible to the output pin (VCOM).
  10. The thermal pad must be soldered to the PCB for correct thermal performance.

10.2 Layout Example

TPS65150-Q1 Layout_01_SLVS576.gif Figure 37. PCB Layout Example