ZHCSI15L June   2006  – May 2018 TPS65023 , TPS65023B

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     简化原理图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Electrical Characteristics: Supply Pins VCC, VINDCDC1, VINDCDC2, VINDCDC3
    7. 6.7  Electrical Characteristics: Supply Pins VBACKUP, VSYSIN, VRTC, VINLDO
    8. 6.8  Electrical Characteristics: VDCDC1 Step-Down Converter
    9. 6.9  Electrical Characteristics: VDCDC2 Step-Down Converter
    10. 6.10 Electrical Characteristics: VDCDC3 Step-Down Converter
    11. 6.11 I2C Timing Requirements for TPS65023B
    12. 6.12 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  VRTC Output and Operation With or Without Backup Battery
      2. 7.3.2  Step-Down Converters, VDCDC1, VDCDC2, and VDCDC3
      3. 7.3.3  Power Save Mode Operation
      4. 7.3.4  Low Ripple Mode
      5. 7.3.5  Soft-Start
      6. 7.3.6  100% Duty Cycle Low Dropout Operation
      7. 7.3.7  Active Discharge When Disabled
      8. 7.3.8  Power-Good Monitoring
      9. 7.3.9  Low-Dropout Voltage Regulators
      10. 7.3.10 Undervoltage Lockout
      11. 7.3.11 Power-Up Sequencing
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 System Reset + Control Signals
        1. 7.5.1.1 DEFLDO1 and DEFLDO2
        2. 7.5.1.2 Interrupt Management and the INT Pin
      2. 7.5.2 Serial Interface
    6. 7.6 Register Maps
      1. 7.6.1 VERSION Register Address: 00h (Read Only)
      2. 7.6.2 PGOODZ Register Address: 01h (Read Only)
      3. 7.6.3 MASK Register Address: 02h (Read and Write), Default Value: C0h
      4. 7.6.4 REG_CTRL Register Address: 03h (Read and Write), Default Value: FFh
      5. 7.6.5 CON_CTRL Register Address: 04h (Read and Write), Default Value: B1h
      6. 7.6.6 CON_CTRL2 Register Address: 05h (Read and Write), Default Value: 40h
      7. 7.6.7 DEFCORE Register Address: 06h (Read and Write), Default Value: 14h/1Eh
      8. 7.6.8 DEFSLEW Register Address: 07h (Read and Write), Default Value: 06h
      9. 7.6.9 LDO_CTRL Register Address: 08h (Read and Write), Default Value: Set with DEFLDO1 and DEFLDO2
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input Voltage Connection
      2. 8.1.2 Unused Regulators
      3. 8.1.3 Reset Condition of DCDC1
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Inductor Selection for the DC-DC Converters
        2. 8.2.2.2 Output Capacitor Selection
        3. 8.2.2.3 Input Capacitor Selection
        4. 8.2.2.4 Output Voltage Selection
        5. 8.2.2.5 VRTC Output
        6. 8.2.2.6 LDO1 and LDO2
        7. 8.2.2.7 TRESPWRON
        8. 8.2.2.8 VCC Filter
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Requirements for Supply Voltages Below 3.0 V
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 第三方产品免责声明
      2. 11.1.2 开发支持
    2. 11.2 文档支持
      1. 11.2.1 相关文档
    3. 11.3 相关链接
    4. 11.4 社区资源
    5. 11.5 商标
    6. 11.6 静电放电警告
    7. 11.7 术语表
  12. 12机械、封装和可订购信息

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • RSB|40
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.5.1.2 Interrupt Management and the INT Pin

The INT pin combines the outputs of the PGOOD comparators from each DC–DC converter and the LDOs. The INT pin is used as a POWER_OK pin to indicate when all enabled supplies are in regulation. The INT pin remains active (low state) during power up as long as all enabled power rails are below their regulation limit. Once the last enabled power rail is within regulation, the INT pin transitions to a high state.

During operation, if one of the enabled supplies goes out of regulation, INT transitions to a low state, and the corresponding bit in the PGOODZ register goes high. If the supply goes back to its regulation limits, INT transitions back to a high state.

While INT is in an active-low state, reading the PGOODZ register through the I2C bus forces INT into a high-Z state. Because this pin requires an external pullup resistor, the INT pin transitions to a logic high state even though the supply in question is still out of regulation. The corresponding bit in the PGOODZ register still indicates that the power rail is out of regulation.

Interrupts can be masked using the MASK register; default operation is not to mask any DCDC or LDO interrupts because this provides the POWER_OK function. If none of the DCDC converters or LDos are enabled, /INT defaults to a low state independently of the settings of the MASK register.