A proper layout is critical for the operation of a switched mode power supply, even more at high switching frequencies. Therefore the PCB layout of the TPS6217x-Q1 demands careful attention to ensure operation and to get the performance specified. A poor layout can lead to issues like poor regulation (both line and load), stability and accuracy weaknesses, increased EMI radiation and noise sensitivity. Considering the following topics ensures best electrical and optimized thermal performance:
1) The input capacitor must be placed as close as possible to the VIN and PGND pin of the IC. This provides low resistive and inductive path for the high di/dt input current.
2) The VOS pin must be connect in the shortest way to VOUT at the output capacitor - avoiding noise coupling.
3) The feedback resistors, R1 and R2 must be connected close to the FB and AGND pins - avoiding noise coupling.
4) The output capacitor should be placed such that its ground is as close as possible to the IC's PGND pins - avoiding additional voltage drop in traces.
5) The inductor should be placed close to the SW pin and connect directly to the output capacitor - minimizing the loop area between the SW pin, inductor, output capacitor and PGND pin.
More detailed information can be found in the EVM Users Guide, SLVU483.
The Exposed Thermal Pad must be soldered to the circuit board for mechanical reliability and to achieve appropriate power dissipation. Although the Exposed Thermal Pad can be connected to a floating circuit board trace, the device will have better thermal performance if it is connected to a larger ground plane. The Exposed Thermal Pad is electrically connected to AGND.
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components affect the power-dissipation limits of a given component.
Three basic approaches for enhancing thermal performance are listed below:
The TPS6217x-Q1 are designed for a maximum operating junction temperature (TJ) of 125°C. Therefore the maximum output power is limited by the power losses that can be dissipated over the actual thermal resistance, given by the package and the surrounding PCB structures. Since the thermal resistance of the package is fixed, increasing the size of the surrounding copper area and improving the thermal connection to the IC can reduce the thermal resistance. To get an improved thermal behavior, it's recommended to use top layer metal to connect the device with wide and thick metal lines. Internal ground layers can connect to vias directly under the IC for improved thermal performance.
If short circuit or overload conditions are present, the device is protected by limiting internal power dissipation.