ZHCS984B June   2012  – May 2019 TPS54678

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化原理图
      2.      效率与输出电流间的关系
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency PWM Control
      2. 7.3.2  Slope Compensation and Output Current
      3. 7.3.3  Bootstrap Voltage (Boot) and Low Dropout Operation
      4. 7.3.4  Error Amplifier
      5. 7.3.5  Voltage Reference
      6. 7.3.6  Adjusting the Output Voltage
      7. 7.3.7  Enable and Adjusting Undervoltage Lockout
      8. 7.3.8  Soft-Start Pin
      9. 7.3.9  Sequencing
      10. 7.3.10 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
      11. 7.3.11 Overcurrent Protection
        1. 7.3.11.1 High-Side Overcurrent Protection
        2. 7.3.11.2 Low-Side Overcurrent Protection
      12. 7.3.12 Safe Start-Up into Prebiased Outputs
      13. 7.3.13 Synchronize Using the RT/CLK Pin
      14. 7.3.14 Power Good (PWRGD Pin)
      15. 7.3.15 Overvoltage Transient Protection
      16. 7.3.16 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Small Signal Model for Loop Response
      2. 7.4.2 Simple Small Signal Model for Peak Current Mode Control
      3. 7.4.3 Small Signal Model for Frequency Compensation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Step One: Select the Switching Frequency
        3. 8.2.2.3 Step Two: Select the Output Inductor
        4. 8.2.2.4 Step Three: Choose the Output Capacitor
        5. 8.2.2.5 Step Four: Select the Input Capacitor
        6. 8.2.2.6 Step Five: Choose the Soft-Start Capacitor
        7. 8.2.2.7 Step Six: Select the Bootstrap Capacitor
        8. 8.2.2.8 Step Eight: Select Output Voltage and Feedback Resistors
          1. 8.2.2.8.1 Output Voltage Limitations
        9. 8.2.2.9 Step Nine: Select Loop Compensation Components
      3. 8.2.3 Application Curves
        1. 8.2.3.1 Additional Information About Application Curves
          1. 8.2.3.1.1 Efficiency
          2. 8.2.3.1.2 Voltage Ripple Measurements
          3. 8.2.3.1.3 Start-Up and Shutdown Waveforms
          4. 8.2.3.1.4 Hiccup Mode Current Limit
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Power Dissipation Estimate
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 第三方产品免责声明
      2. 11.1.2 开发支持
        1. 11.1.2.1 使用 WEBENCH® 工具创建定制设计
    2. 11.2 文档支持
      1. 11.2.1 相关文档
    3. 11.3 接收文档更新通知
    4. 11.4 社区资源
    5. 11.5 商标
    6. 11.6 静电放电警告
    7. 11.7 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.4.2 Simple Small Signal Model for Peak Current Mode Control

Figure 26 is a simple small signal model that can be used to understand how to design the frequency compensation. The TPS54678 power stage can be approximated to a voltage controlled current source (duty cycle modulator) supplying current to the output capacitor and load resistor. The control to output transfer function is shown in Equation 6 and consists of a DC gain, one dominant pole and one ESR zero. The quotient of the change in switch current and the change in COMP pin voltage (node c in Figure 26) is the power stage transconductance. The gm for the TPS54678 is 20 A/V. The low-frequency gain of the power stage frequency response is the product of the transconductance and the load resistance as shown in Equation 7. As the load current increases and decreases, the low-frequency gain decreases and increases, respectively. This variation with load may seem problematic at first glance, but fortunately the dominant pole moves with load current (see Equation 8). The combined effect is highlighted by the dashed line in Figure 28. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover frequency the same for the varying load conditions, which makes it easier to design the frequency compensation.

TPS54678 sds_freq_resp_schem_slvsa70.gifFigure 27. Small Signal Model For Peak Current Mode Control
TPS54678 sds_freq_resp_wave_slvsa70.gifFigure 28. Frequency Response Model for Peak Current Mode Control
Equation 6. TPS54678 eq6_lvsbf3.gif
Equation 7. TPS54678 eq7_lvsbf3.gif
Equation 8. TPS54678 eq8_lvsbf3.gif
Equation 9. TPS54678 eq9_lvsbf3.gif