ZHCSCI5B 数据表 | 德州仪器 TI.com.cn

ZHCSCI5B May 2014 – July 2016 TPS544B20 , TPS544C20

PRODUCTION DATA.

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机械数据 (封装 | 引脚)

RVF|40
- MPQF268C

散热焊盘机械数据 (封装 | 引脚)

RVF|40
- QFND333E

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) See ⁽¹⁾⁽²⁾⁽³⁾

		MIN	MAX	UNIT
Input voltage	VIN, VDD	–0.3	20	V
	BOOT	–0.3	37
	BOOT – SW (BOOT to SW differential)	–0.3	7
	CLK, DATA	–0.3	3.6
	FB, SYNC, CNTL, VOUTS–, VOUTS+, BPEXT	–0.3	7
Output voltage	BP6	–0.3	7	V
	SW	–1	30
	SW ( > 50 ns, > 10 µJ)	-5	30
	COMP, DIFFO, SMBALERT, PGOOD	–0.3	7
	ADDR0, ADDR1, BP3, RT, TSNS	–0.3	3.6
T_J, operating junction temperature		–40	150	°C
T_stg, Storage temperature		–55	150	°C

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Operating Ratings is not implied. The recommended Operating Ratings indicate conditions at which the device is functional and the device should not be operated beyond such conditions.

(2) The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin.

(3) If Military or Aerospace specified devices are required, contact the Texas Instruments Sales/Office/Distributors for availability and specifications.

7.2 ESD Ratings

			VALUE		UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	±2000		V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	±500		V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
V_DD	Controller input voltage	4.5	18	V
V_IN	Power stage input voltage	4.5	18	V
T_J	Junction temperature	–40	125	°C

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPS544B20 TPS544C20	UNIT
R_θJA	Junction-to-ambient thermal resistance⁽²⁾	27.5	°C/W
R_θJCtop	Junction-to-case (top) thermal resistance⁽³⁾	13.9	°C/W
R_θJB	Junction-to-board thermal resistance	4.0	°C/W
ψ_JT	Junction-to-top characterization parameter⁽⁴⁾	0.3	°C/W
ψ_JB	Junction-to-board characterization parameter⁽⁵⁾	3.9	°C/W
R_θJCbot	Junction-to-case (bottom) thermal resistance⁽⁶⁾	0.9	°C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining R_θJA, using a procedure described in JESD51-2a (sections 6 and 7).

(5) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining R_θJA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

7.5 Electrical Characteristics

T_J = –40°C to 125°C, V_IN = V_VDD= 12 V, R_RT = 38.3 kΩ; zero power dissipation (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
INPUT SUPPLY
V_VDD	Input supply voltage range			4.5		18	V
V_VIN	Power stage voltage range			4.5		18	V
I_VDD	Input Operating Current	Not switching				10	mA
UVLO
V_IN(on)	Input turn on voltage	Default settings		4.05	4.25	4.45	V
V_IN(off)	Input turn off voltage	Default settings		3.8	4	4.2	V
V_INON(rng)	Programmable range for turn-on voltage			4.25		16	V
V_INOFF(rng)	Programmable range for turn-off voltage			4		15.75	V
ERROR AMPLIFIER AND FEEDBACK VOLTAGE
V_FB	Feedback Voltage	0°C ≤ T_J ≤ 70°C		597	600	603	mV
V_FB	Feedback Voltage	–40°C ≤ T_J ≤ 125°C		594	600	606	mV
g_M	Transconductance				130		µS
I_FB	FB pin bias current (out of pin)	V_FB = 0.6 V				50	nA
V_{LOOP_COMP}	Loop comparator offset voltage	V_FB = 0.6 V, T_J = 25°C		-7.5		7.5	mV
BP6 REGULATOR
V_BP6	Output voltage	I_BP6 = 10 mA		6.2	6.5	6.8	V
V_BP6(do)	Dropout voltage	V_VIN – V_BP6, V_VDD = 4.5 V, I_BP6 = 25 mA				100	mV
I_BP6	Output current⁽¹⁾	V_VDD = 12 V		120			mA
V_BP6UV	Regulator UVLO voltage⁽¹⁾			3.3	3.55	3.8	V
V_BP6UV(hyst)	Regulator UVLO voltage hysteresis⁽¹⁾			230	255	270	mV
BPEXT
V_{BPEXT(swover)}	BPEXT switch-over voltage	VDD > V_IN(on)		4.5	4.65		V
V_hys(swover)	BPEXT switch-over hysteresis			100		200	mV
V_BPEXT(do)	BPEXT dropout voltage	V_BPEXT -V_BP6, V_BPEXT = 4.8 V, I_BP6 = 25 mA				100	mV
BOOTSTRAP
V_BOOT(drop)	Bootstrap voltage drop	I_BOOT = 5 mA				150	mV
BP3 REGULATOR
V_BP3	Output voltage	V_VDD = 4.5 V, I_BP3 ≤ 5 mA		3.1	3.3	3.5	V
SOFT START
t_SS	Soft-start time⁽³⁾	Factory default settings			2.7		ms
	Programmable range⁽¹⁾			0.6		9	ms
	Accuracy over range⁽¹⁾				±10%
t_ON(DELAY)	Turn-on delay	Factory default settings			0		ms
t_OFF(DELAY)	Turn-off delay	Factory default settings			0		ms
REMOTE SENSE AMPLIFIER
V_DIFFO(ERROR)	Error voltage from DIFFO to V_SNS	(V_OUTS+ – V_OUTS–) = 0.6 V		-5		5	mV
		(V_OUTS+ – V_OUTS–) = 1.2 V		-8		8
		(V_OUTS+ – V_OUTS–) = 3.0 V		-17		17
BW	Closed-loop bandwidth⁽¹⁾			2			MHz
R_VOUTx	Output voltage sense input impedance	V_OUT+ = 1.2V		55	80	105	kΩ
V_DIFFO(max)	Maximum DIFFO output voltage			V_BP6-0.2			V
I_DIFFO	DIFFO sourcing current			1			mA
I_DIFFO	DIFFO sinking current			1			mA
POWER STAGE
R_HS	High-side on-resistance	V_VDD = 4.5 V, T_J = 25°C			4.9		mΩ
R_HS	High-side on-resistance	V_VDD ≥ 12 V, T_J = 25°C			4.5		mΩ
I_HS(leak)	High-side leakage current	V_VDD = 18 V, T_J = 25°C			0.4	0.7	µA
I_HS(leak)	High-side leakage current	V_VDD = 18 V, T_J = 125°C⁽¹⁾			1.5		µA
R_LS	Low-side on-resistance	V_VDD = 4.5 V, T_J = 25°C			2.2		mΩ
R_LS	Low-side on-resistance	V_VDD ≥ 12 V, T_J = 25°C			2.0		mΩ
CURRENT LIMIT
t_OFF(OC)	Off time between restart attempts	Hiccup mode			7 × t_SS		ms
I_OC(flt)	Output current overcurrent fault threshold	Factory default settings	TPS544B20		26		A
		Programmable range	TPS544B20	5		30
		Factory default settings	TPS544C20		39
		Programmable range	TPS544C20	5		45
I_OC(warn)	Output current overcurrent warning threshold	Factory default settings	TPS544B20		20		A
		Programmable range	TPS544B20	4		29.5
		Factory default settings	TPS544C20		30
		Programmable range	TPS544C20	4		44.5
I_OC(acc)	Output current overcurrent fault and warning accuracy	I_OCF = 20 A⁽¹⁾			±3		A
t_LSOC(min)	Minimum LDRV pulse width for valid current sensing⁽¹⁾				400	500	ns
HIGH-SIDE SHORT CIRCUIT PROTECTION
I_HSOC	High-side short-circuit protection fault threshold	T_J = 25°C	TPS544B20	30		58	A
I_HSOC	High-side short-circuit protection fault threshold	T_J = 25°C	TPS544C20	45		75	A
POWER GOOD (PGOOD)
V_FBPGH	FB PGOOD high threshold	Factory default settings			675		mV
V_FBPGL	FB PGOOD low threshold	Factory default settings			525		mV
V_PG(acc)	PGOOD accuracy over range	Factory default settings		–5%		5%
V_pg(hyst)	FB PGOOD hysteresis voltage			10		50	mV
R_PGOOD	PGOOD pull-down resistance	V_FB = 0, I_PGOOD = 5 mA			30	70	Ω
I_PGOOD(lk)	PGOOD pin leakage current	Factory default settings, V_PGOOD = 5 V				20	µA
OUTPUT OVERVOLTAGE AND UNDERVOLTAGE PROTECTION
V_FBOV	FB pin over voltage threshold	Factory default settings			700		mV
V_FBUV	FB pin under voltage threshold	Factory default settings			499		mV
V_UVOV(acc)	FB UV, OV accuracy over range	Factory default settings		–4.5%		4.5%
OUTPUT VOLTAGE TRIMMING AND MARGINING
V_FBTM(step)	Resolution of FB steps with trim and margin				2		mV
t_FBTM(step)	Transition time per trim or margin step	After soft-start time			30		µs
V_FBTM(max)	Maximum FB voltage with trim or margin only				660		mV
V_FBTM(min)	Minimum FB voltage with trim or margin only				480		mV
V_FBTM(rng)	FB voltage range with trim and margin combined			420		660	mV
V_FBMH	Margin high FB pin voltage	Factory default settings			660		mV
V_FBML	Margin low FB pin voltage	Factory default settings			540		mV
TEMPERATURE SENSE AND THERMAL SHUTDOWN
T_SD	Junction shutdown temperature⁽¹⁾			135	145	155	°C
T_HYST	Thermal shutdown hysteresis⁽¹⁾			20	25	30	°C
I_TSNS(ratio)	Ratio of bias current flowing out of TSNS pin, state 2 to state 1			9.7	10.0	10.3	µA/µA
I_TSNS	State 1 current out of TSNS pin				10		µA
I_TSNS	State 2 current out of TSNS pin				100		µA
V_TSNS	Voltage range on TSNS pin⁽¹⁾			0		1.00	V
T_OT(flt)	Overtemperature fault limit⁽¹⁾	Factory default settings			150		°C
T_OT(flt)	OT fault limit range⁽¹⁾			120		165	°C
T_OT(warn)	Overtemperature warning limit⁽¹⁾	Factory default settings			125		°C
T_OT(warn)	OT warning limit range⁽¹⁾			100		140	°C
T_OT(step)	OT fault, warning step⁽¹⁾				5		°C
T_OT(hys)	OT fault, warning hysteresis⁽¹⁾			15	20	25	°C
MEASUREMENT SYSTEM
M_VOUT(rng)	Output voltage measurement range			0.5		5.8	V
M_VOUT(acc)	Output voltage measurement accuracy			–2.0%		2.0%
M_VOUT(lsb)	Output voltage measurement bit resolution				1.95		mV
M_IOUT(acc)	Output current measurement accuracy⁽²⁾	I_OUT ≥ 20 A, -40 ≤ T_A ≤ 85°C		-15%		+15%
M_IOUT(acc)	Output current measurement accuracy⁽²⁾	3 A ≤ I_OUT < 20 A, –40 ≤ T_A ≤ 85°C		-3		+3	A
M_IOUT(lsb)	Output current measurement bit resolution⁽¹⁾				62.5		mA
M_TSNS(rng)	External temperature sense range⁽¹⁾			-40		165	°C
M_TSNS(acc)	External temperature sense accuracy⁽¹⁾	-40°C ≤ T_J(sensor) ≤ 165°C		-8		8	°C
M_TSNS(lsb)	External temperature sense bit resolution⁽¹⁾				1.238		°C
PMBus INTERFACE ADDRESSING
I_ADD	Address pin bias current			8.23	9.75	11.21	µA
V_ADD(rng)	Address pin legal address voltage range			0.08		2.35	V

(1) Specified by design. Not production tested.

(2) Current sense amplifier gain and offset are production tested. Output current monitoring guaranteed by correlation.

(3) Soft-start time is defined by the rise time of the internal reference, V_REF

7.6 Switching Characteristics

V_IN = V_DD = 12 V, T_A = 25 ºC, R_RT = 38.3 kΩ (unless otherwise specified).

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
TON GENERATOR AND SW TIMING
f_SW	Switching frequency⁽¹⁾	Adjustment range	250		1000	kHz
		R_RT = 10.0 kΩ	210	250	290
		R_RT = 17.8 kΩ	250	300	350
		R_RT = 27.4 kΩ	340	400	460
		R_RT = 38.3 kΩ	425	500	575
		R_RT = 56.2 kΩ	550	650	750
		R_RT = 86.6 kΩ	640	750	860
		R_RT = 133 kΩ	720	850	980
		R_RT = 205 kΩ	850	1000	1150
I_RT	RT output current			9.75		µA
t_OFF(min)	Minimum off-time⁽¹⁾ ⁽²⁾			175		ns
t_ON(min)	Minimum controllable pulse width⁽¹⁾				80	ns
V_DCAP2	D-CAP2 mode threshold				2.10	V
V_DCAP	D-CAP mode threshold		0.8			V
I_MODE	MODE output current		7		13	µA
t_DEAD	Power stage driver dead-time⁽¹⁾	SW rising		15		ns
t_DEAD	Power stage driver dead-time⁽¹⁾	SW falling		15		ns
t_SLEW(SW)	SW slew rate⁽¹⁾	SW rising (10% to 90%), I_OUT = 30 A, R_BOOT= 0 Ω		9.2		V/ns
t_SLEW(SW)	SW slew rate⁽¹⁾	SW falling (90% to 10%), I_OUT = 30 A, R_BOOT= 0 Ω		6.2		V/ns

(1) On-times are production tested, but steady-state switching frequency is not.

(2) Minimum off time for valid current sensing is 400-ns typical, 500-ns maximum.

7.7 Typical Characteristics

V_IN = V_DD = 12 V, T_A = 25 ºC, R_RT = 38.3 kΩ (unless otherwise specified). Safe operating area curves were measured using a Texas Instruments Evaluation Module.