ZHCSAO5B December   2012  – October 2015 TPS51604

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
    7. 6.7 Typical Power Block MOSFET Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 UVLO Protection
      2. 7.3.2 PWM Pin
      3. 7.3.3 SKIP Pin
        1. 7.3.3.1 Zero Crossing (ZX) Operation
      4. 7.3.4 Adaptive Dead-Time Control and Shoot-Through Protection
      5. 7.3.5 Integrated Boost-Switch
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Step 1: Select the Input (VDD) Capacitor
        2. 8.2.2.2 Step 2: Select Boot Capacitor and Boot Resistor
        3. 8.2.2.3 Step 3: Establish Connection Between TPS51604 and Controller
        4. 8.2.2.4 Step 4: Establish Connection Between TPS51604 and the Power Block
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 开发支持
    2. 11.2 文档支持
      1. 11.2.1 相关文档
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

DSG Package
8-Pin WSON
Top View
TPS51604 pinout_dsg8_slusba6.gif

Pin Functions

PIN I/O(1) DESCRIPTION
NAME NO.
BST 1 I High-side N-channel FET bootstrap voltage input; power supply for high-side driver
DRVH 8 O High-side N-channel gate drive output
DRVL 5 O Synchronous low-side N-channel gate drive output
GND 6 G Synchronous low-side N-channel gate drive return and device reference
PWM 2 I PWM input. A tri-state voltage on this pin turns off both the high-side (DRVH) and low-side drivers (DRVL)
SKIP 3 I When SKIP is LO, the zero crossing comparator is active. The power chain enters discontinuous conduction mode when the inductor current reaches zero. When SKIP is HI, the zero crossing comparator is disabled, and the driver outputs follow the PWM input. A tri-state voltage on SKIP puts the driver into a very-low power state.
SW 7 I/O High-side N-channel gate drive return. Also, zero-crossing sense input
VDD 4 I 5-V power supply input; decouple to GND with a ceramic capacitor with a value of 1 µF or greater
Thermal Pad G Tie to system GND plane with multiple vias
(1) I = Input, O = Output, G = Ground