ZHCSK23A July   2019  – September 2019 TPS3870-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      集成过压检测
      2.      典型过压精度分布
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VDD
      2. 8.3.2 SENSE
      3. 8.3.3 RESET
      4. 8.3.4 Capacitor Time (CT)
      5. 8.3.5 Manual Reset (MR)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation (VDD > VDD(MIN))
      2. 8.4.2 Undervoltage Lockout (VPOR < VDD < UVLO)
      3. 8.4.3 Power-On Reset (VDD < VPOR)
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Voltage Threshold Accuracy
      2. 9.1.2 CT Reset Time Delay
        1. 9.1.2.1 Factory-Programmed Reset Delay Timing
        2. 9.1.2.2 Programmable Reset Delay-Timing
      3. 9.1.3 RESET Latch Mode
      4. 9.1.4 Adjustable Voltage Thresholds
      5. 9.1.5 Immunity to SENSE Pin Voltage Transients
        1. 9.1.5.1 Hysteresis
    2. 9.2 Typical Application
      1. 9.2.1 Design 1: RESET Latch Mode
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Guidelines
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 器件命名规则
    2. 12.2 文档支持
      1. 12.2.1 评估模块
    3. 12.3 接收文档更新通知
    4. 12.4 支持资源
    5. 12.5 商标
    6. 12.6 静电放电警告
    7. 12.7 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Pin Configuration and Functions

DSE Package
6-Pin WSON
Top View
TPS3870-Q1 DSE-6-Package-Drawing.gif

Pin Functions

PIN I/O DESCRIPTION
NO. NAME
1 SENSE I Input for the monitored supply voltage rail. When the SENSE voltage goes above the overvoltage threshold, the RESET pin is driven low. Connect to VDD pin if monitoring VDD supply voltage.
2 VDD I Supply voltage input pin. Good analog design practice is to place a 0.1-μF ceramic capacitor close to this pin.
3 CT I Capacitor time delay pin. The CT pin offers two fixed time delays by connecting CT pin to VDD or leaving it floating. Delay time can be programmed by connecting an external capacitor reference to ground.
4 RESET O Active-low, open-drain output. This pin goes low when the SENSE voltage rises above the internally overvoltage threshold (VIT+). See the timing diagram in Figure 19 for more details. Connect this pin to a pull-up resistor terminated to the desired pull-up voltage.
5 GND — Ground
6 MR I Manual reset (MR), pull this pin to a logic low (VMR_L) to assert a reset signal . After the MR pin is deasserted the output goes high after the reset delay time(tD) expires. MR can be left floating when not in use.