ZHCSCJ3D June   2014  – October  2017 TPS25942A , TPS25942L , TPS25944A , TPS25944L

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用范围
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Enable and Adjusting Undervoltage Lockout
      2. 9.3.2  Overvoltage Protection (OVP)
      3. 9.3.3  Hot Plug-In and In-Rush Current Control
      4. 9.3.4  Overload and Short Circuit Protection
        1. 9.3.4.1 Overload Protection
        2. 9.3.4.2 Short Circuit Protection
        3. 9.3.4.3 Start-Up With Short on Output
        4. 9.3.4.4 Constant Current Limit Behavior During Overcurrent Faults
      5. 9.3.5  Reverse Current Protection
      6. 9.3.6  FAULT Response
      7. 9.3.7  Current Monitoring
      8. 9.3.8  Power Good Comparator
      9. 9.3.9  IN, OUT and GND Pins
      10. 9.3.10 Thermal Shutdown
    4. 9.4 Device Functional Modes
      1. 9.4.1 Diode Mode
      2. 9.4.2 Shutdown Control
      3. 9.4.3 Operational Differences Between the TPS25942 and TPS25944
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Step by Step Design Procedure
        2. 10.2.2.2 Programming the Current-Limit Threshold: R(ILIM) Selection
        3. 10.2.2.3 Undervoltage Lockout and Overvoltage Set Point
        4. 10.2.2.4 Programming Current Monitoring Resistor—RIMON
        5. 10.2.2.5 Setting Output Voltage Ramp Time (tdVdT)
          1. 10.2.2.5.1 Case1: Start-Up Without Load: Only Output Capacitance C(OUT) Draws Current During Start-Up
          2. 10.2.2.5.2 Case 2: Start-Up With Load: Output Capacitance C(OUT) and Load Draws Current During Start-Up
        6. 10.2.2.6 Programing the Power Good Set Point
        7. 10.2.2.7 Support Component Selections—R6, R7 and CIN
      3. 10.2.3 Application Curves
    3. 10.3 System Examples
      1. 10.3.1 Active ORing (Auto-Power Multiplexer) Operation
        1. 10.3.1.1 N+1 Power Supply Operation
        2. 10.3.1.2 Priority Power MUX Operation
        3. 10.3.1.3 Priority MUXing With Almost Equal Rails (VIN1 ~ VIN2)
        4. 10.3.1.4 Reverse Polarity Protection
  11. 11Power Supply Recommendations
    1. 11.1 Transient Protection
    2. 11.2 Output Short-Circuit Measurements
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13器件和文档支持
    1. 13.1 器件支持
    2. 13.2 文档支持
      1. 13.2.1 相关文档
    3. 13.3 相关链接
    4. 13.4 接收文档更新通知
    5. 13.5 社区资源
    6. 13.6 商标
    7. 13.7 静电放电警告
    8. 13.8 Glossary
  14. 14机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7 Specifications

7.1 Absolute Maximum Ratings

over operating temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Input voltage IN, OUT, PGTH, PGOOD, EN, OVP, DMODE, FLT –0.3 20 V
IN (10-ms transient) 22
dVdT, ILIM –0.3 3.6
IMON –0.3 7
Sink current PGOOD, FLT, dVdT 10 mA
Source current dVdT, ILIM, IMON Internally Limited
Continuous power dissipation See the Thermal Information
TJ Maximum junction temperature –40 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
VESD Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001s(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Input voltage IN 2.7 18 V
EN, OVP, DMODE, OUT, PGTH, PGOOD, FLT 0 18
dVdT, ILIM 0 3
IMON 0 6
Resistance ILIM 16.9 150 kΩ
IMON 1
External capacitance OUT 0.1 µF
dVdT 470 nF
TJ Operating junction temperature –40 25 125 °C

7.4 Thermal Information

THERMAL METRIC(1) TPS25942
TPS25944		 UNIT
RVC (WQFN)
20 PINS
RθJA Junction-to-ambient thermal resistance 38.1 °C/W
RθJCtop Junction-to-case (top) thermal resistance 40.5 °C/W
RθJB Junction-to-board thermal resistance 13.6 °C/W
ψJT Junction-to-top characterization parameter 0.6 °C/W
ψJB Junction-to-board characterization parameter 13.7 °C/W
RθJCbot Junction-to-case (bottom) thermal resistance 3.4 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics

Conditions are –40°C ≤ TJ = TA ≤ +125°C, 2.7 V ≤ V(IN) ≤ 18 V, V(EN/UVLO) = 2 V, V(OVP) = V(DMODE) = V(PGTH) = 0 V, R(ILIM) = 150 kΩ, C(OUT) = 1 µF, C(dVdT) = OPEN, PGOOD = FLT = IMON = OPEN. Positive current into terminals. All voltages referenced to GND (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE AND INTERNAL UNDERVOLTAGE LOCKOUT
V(IN) Operating input voltage 2.7 18 V
V(UVR) Internal UVLO threshold, rising 2.2 2.3 2.4 V
V(UVRhys) Internal UVLO hysteresis 105 116 125 mV
IQ(ON) Supply current, enabled V(EN/UVLO) = 2 V, V(IN) = 3 V 140 210 300 µA
V(EN/UVLO) = 2 V, V(IN) = 12 V 140 199 260
V(EN/UVLO) = 2 V, V(IN) = 18 V 140 202 270
IQ(OFF) Supply current, disabled V(EN/UVLO) = 0 V, V(IN) = 3 V 4 8.6 15 µA
V(EN/UVLO) = 0 V, V(IN) = 12 V 6 15 20
V(EN/UVLO) = 0 V, V(IN) = 18 V 8 18.5 25
ENABLE AND UNDERVOLTAGE LOCKOUT (EN/UVLO) INPUT
V(ENR) EN/UVLO threshold voltage, rising 0.97 0.99 1.01 V
V(ENF) EN/UVLO threshold voltage, falling 0.9 0.92 0.94 V
V(SHUTF) EN threshold voltage for Low IQ shutdown, falling 0.3 0.47 0.63 V
V(SHUTFhys) EN hysteresis for low IQ shutdown, hysteresis(1) 66 mV
IEN EN input leakage current 0 V ≤ V(EN/UVLO) ≤ 18 V –100 0 100 nA
OVER VOLTAGE PROTECTION (OVP) INPUT
V(OVPR) Overvoltage threshold voltage, rising 0.97 0.99 1.01 V
V(OVPF) Overvoltage threshold voltage, falling 0.9 0.92 0.94 V
I(OVP) OVP input leakage current 0 V ≤ V(OVP) ≤ 5 V –100 0 100 nA
DIODE MODE INPUT (DMODE)—ACTIVE HIGH
V(DMODE) DMODE threshold voltage, rising 1.6 1.85 2 V
DMODE threshold voltage, falling 0.8 0.96 1.1 V
I(DMODE) DMODE input leakage current 0.2 V ≤ V(DMODE) ≤ 18 V 0.6 1 1.25 µA
OUTPUT RAMP CONTROL (dVdT)
I(dVdT) dVdT charging current V(dVdT) = 0 V 0.85 1 1.15 µA
R(dVdT) dVdT discharging resistance EN/UVLO = 0 V, I(dVdT) = 10 mA sinking 16 24 Ω
V(dVdTmax) dVdT maximum capacitor voltage 2.6 2.88 3.1 V
GAIN(dVdT) dVdT to OUT gain ΔV(OUT)/ΔV(dVdT) 11.65 11.9 12.05 V/V
CURRENT LIMIT PROGRAMMING (ILIM)
V(ILIM) ILIM bias voltage 0.87 V
I(LIM) Current limit
I(LIM) for TPS25942(2)
I(FAULT) forTPS25944 (2)(3)		 R(ILIM) = 150 kΩ, (V(IN) – V(OUT))  = 1 V 0.53 0.58 0.63 A
R(ILIM) = 88.7 kΩ, (V(IN) – V(OUT))  = 1 V 0.9 0.99 1.07
R(ILIM) = 42.2 kΩ, (V(IN) – V(OUT)) = 1 V 1.92 2.08 2.25
R(ILIM) = 24.9 kΩ, (V(IN) – V(OUT)) = 1 V 3.25 3.53 3.81
R(ILIM) = 20 kΩ, (V(IN) – V(OUT))  = 1 V 4.09 4.45 4.81
R(ILIM) = 16.9 kΩ, (V(IN) – V(OUT))  = 1 V 4.78 5.2 5.62
R(ILIM) = OPEN, open resistor current limit (single point failure test: UL60950) 0.35 0.45 0.55
R(ILIM) = SHORT, shorted resistor current limit (single point failure test: UL60950) 0.55 0.67 0.8
DMODE = High; Non-ideal diode mode(1) 0.5 × I(LIM)
I(OS) Short-circuit current limit R(ILIM) = 42.2 kΩ, V(VIN) = 12 V, (V(IN) – V(OUT)) = 5 V 1.91 2.07 2.24 A
R(ILIM) = 24.9 kΩ, V(VIN) = 12 V, (V(IN) – V(OUT)) = 5 V 3.21 3.49 3.77
R(ILIM) = 16.9 kΩ, V(VIN) = 12 V, (V(IN) – V(OUT)) = 5 V,
–40°C ≤ TJ ≤ +85°C 		4.7 5.11 5.52
I(FASTRIP) Fast-trip comparator threshold(1)(2) 1.5 × I(LIM) + 0.375 A
CURRENT MONITOR OUTPUT (IMON)
GAIN(IMON) Gain factor I(IMON):I(OUT) 1 A ≤ I(OUT) ≤ 5 A 47.78 52.3 57.23 µA/A
MOSFET—POWER SWITCH
RON IN to OUT - ON resistance 1 A ≤ I(OUT) ≤ 5 A, TJ = 25°C 34 42 49 mΩ
1 A ≤ I(OUT) ≤ 5 A, –40°C ≤ TJ ≤ +85°C 26 42 58
1 A ≤ I(OUT) ≤ 5 A, –40°C ≤ TJ ≤ +125°C 26 42 64
PASS FET OUTPUT (OUT)
Ilkg(OUT) OUT leakage current in off state V(IN) = 18 V, V(EN/UVLO) = 0 V, V(OUT) = 0 V (sourcing) –2 0 2 µA
V(IN) = 2.7 V, V(EN/UVLO) = 0 V, V(OUT) = 18 V (sinking) 6 13 20
V(REVTH) V(IN) – V(OUT) threshold for reverse protection comparator, falling –15 –9.3 –3 mV
V(FWDTH) V(IN) – V(OUT) threshold for reverse protection comparator, rising 86 100 114 mV
FAULT FLAG (FLT)—ACTIVE LOW
R(FLT) FLT internal pull-down resistance V(OVP) = 2 V, I(FLT) = 5 mA sinking 10 18 30 Ω
I(FLT) FLT input leakage current 0 V ≤ V(FLT) ≤ 18 V –1 0 1 µA
POSITIVE INPUT for POWER-GOOD COMPARATOR (PGTH)
V(PGTHR) PGTH threshold voltage, rising 0.97 0.99 1.01 V
V(PGTHF) PGTH threshold voltage, falling 0.9 0.92 0.94 V
I(PGTH) PGTH input leakage current 0 V ≤ V(PGTH) ≤ 18 V –100 0 100 nA
POWER-GOOD COMPARATOR OUTPUT (PGOOD): ACTIVE HIGH
R(PGOOD) PGOOD internal pull-down resistance V(PGTH) = 0V, I(PGOOD) = 5 mA sinking 10 20 35 Ω
I(PGOOD) PGOOD input leakage current 0 V ≤ V(PGOOD) ≤ 18 V –1 0 1 µA
THERMAL SHUT DOWN (TSD)
T(TSD) TSD threshold(1) 160 °C
T(TSDhys) TSD hysteresis(1) 12 °C
Thermal fault: (latched or auto-retry) TPS25942L, TPS25944L Latched
TPS25942A, TPS25944A Auto-retry
(1) These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's product warranty.
(2) Pulse-testing techniques maintain junction temperature close to ambient temperature. Thermal effects must be taken into account separately.
(3) The TPS25942 limits current to the programmed I(LIM) level. TPS25944 does not limit current but runs the fault timer when I(LOAD) > I(LIM).

7.6 Timing Requirements

Conditions are –40°C ≤ TJ = TA ≤ +125°C, 2.7 V ≤ V(IN) ≤ 18 V, V(EN/UVLO) = 2 V, V(OVP) = V(DMODE) = V(PGTH) = 0 V, R(ILIM) = 150 kΩ, C(OUT) = 1 µF, C(dVdT) = OPEN, PGOOD = FLT = IMON = OPEN. Positive current into terminals. All voltages referenced to GND (unless otherwise noted). See Figure 47 for timing diagrams.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ENABLE AND UVLO INPUT
tON(dly) EN turnon delay EN/UVLO ↑ (100 mV above V(ENR)) to V(OUT) = 100 mV,
C(dVdT) < 0.8 nF		 220 µs
EN/UVLO ↑ (100 mV above V(ENR)) to V(OUT) = 100 mV,
C(dVdT) ≥ 0.8 nF, see , [C(dVdT) in nF]		 100 + 150 × C(dVdT) µs
tOFF(dly) EN turnoff delay EN/UVLO ↓ (100 mV below V(ENF)) to FLT↓ 2 µs
OVERVOLTAGE PROTECTION INPUT (OVP)
tOVP(dly) OVP disable delay OVP↑ (100 mV above V(OVPR)) to FLT↓ 2 µs
DIODE MODE INPUT: ACTIVE HIGH (DMODE)
tDMODE DMODE turnon delay DMODE↓ to (V(IN) – V(OUT)) ≤ 200 mV, with 1 A resistive load at OUT 2 µs
DMODE turnoff delay DMODE↑ to (V(IN) – V(OUT)) > 200 mV, 1 A resistive load at OUT 220 ns
OUTPUT RAMP CONTROL (dVdT)
tdVdT Output ramp time EN/UVLO ↑ to V(OUT) = 4.5 V, with C(dVdT) = open 0.12 ms
EN/UVLO ↑ to V(OUT) = 11 V, with C(dVdT) = open 0.25 0.37 0.5
EN/UVLO↑ to V(OUT) = 11 V, with C(dVdT) = 1 nF 0.97
CURRENT LIMIT
tFASTRIP(dly) Fast-trip comparator delay I(OUT) > I(FASTRIP) 200 ns
REVERSE PROTECTION COMPARATOR
tREV(dly) Reverse protection comparator delay (V(IN) – V(OUT))↓ (1 mV overdrive below V(REVTH)) to FLT↓ 10 µs
(V(IN) – V(OUT))↓ (10 mV overdrive below V(REVTH)) to FLT↓ 1
tFWD(dly) (V(IN) – V(OUT))↑ (10 mV overdrive above V(FWDTH)) to FLT↑ 3.1
POWER-GOOD COMPARATOR OUTPUT (PGOOD): ACTIVE HIGH
tPGOODR PGOOD delay (de-glitch) time TPS25942: rising edge 0.42 0.54 0.66 ms
TPS25944: rising edge 4
tPGOODF TPS25942 and TPS25944: falling edge 10 µs
FAULT FLAG (FLT)
tCB(dly) FLT assertion delay in circuit breaker mode TPS25944 only; delay from I(OUT) > I(LIM) to FLT↓ (and internal FET turned off) 4 ms
tCB(Retrydly) Retry delay in circuit breaker mode TPS25944A only; circuit breaker fault asserted, delay from to FLT↓ to FLT↑ edge 128 ms
THERMAL SHUT DOWN (TSD)
Retry delay in TSD TPS25942A and TPS25944A only 128 ms

7.7 Typical Characteristics

Conditions are –40°C ≤ TJ = TA ≤ +125°C, V(IN) = 12 V, V(EN/UVLO) = 2 V, V(OVP) = V(DMODE) = V(PGTH) = 0 V, R(ILIM) = 150 kΩ, C(OUT) = 1 µF, C(dVdT) = OPEN, PGOOD = FLT = IMON = OPEN. (unless stated otherwise)
TPS25942A TPS25942L TPS25944A TPS25944L C001_SLVSCE9.png
Figure 1. Internal UVLO Threshold Voltage vs Temperature
TPS25942A TPS25942L TPS25944A TPS25944L D003_SLVSCE9.gif
Figure 3. Input Supply Current vs Supply Voltage at Shutdown
TPS25942A TPS25942L TPS25944A TPS25944L C005_SLVSCE9.png
Figure 5. OVP Threshold Voltage vs Temperature
TPS25942A TPS25942L TPS25944A TPS25944L C007_SLVSCE9.png
Figure 7. EN Threshold Voltage for Low IQ Mode vs Temperature
TPS25942A TPS25942L TPS25944A TPS25944L C009_SLVSCE9.png
Figure 9. Enable Turnoff Delay vs Temperature
TPS25942A TPS25942L TPS25944A TPS25944L D204_SLVSCE9.gif
Figure 11. DMODE Threshold Voltage vs Temperature
TPS25942A TPS25942L TPS25944A TPS25944L C013_SLVSCE9.png
Figure 13. GAIN(dVdT) vs Temperature
TPS25942A TPS25942L TPS25944A TPS25944L C015_SLVSCE9.png
Figure 15. Current Limit vs Current Limit Resistor
TPS25942A TPS25942L TPS25944A TPS25944L D017_SLVSCE9.gif
Figure 17. Current Limit vs Temperature Across R(ILIM)
TPS25942A TPS25942L TPS25944A TPS25944L D030_SLVSCE9.gif
For I(LIM) = 5.3 A, device goes into thermal shutdown for
[V(IN) – V(OUT)] > 8 V
Figure 19. Current Limit Normalized (%) vs V(IN) – V(OUT)
TPS25942A TPS25942L TPS25944A TPS25944L C022_SLVSCE9.png
Figure 21. Fast Trip Threshold vs Current Limit
TPS25942A TPS25942L TPS25944A TPS25944L C023_SLVSCE9.png
Figure 23. GAIN(IMON) vs Temperature
TPS25942A TPS25942L TPS25944A TPS25944L D025_SLVSCE9.gif
Figure 25. RON vs Temperature Across Load Current
TPS25942A TPS25942L TPS25944A TPS25944L C102_SLVSCE9.png
Figure 27. V(REVTH) vs Temperature
TPS25942A TPS25942L TPS25944A TPS25944L C104_SLVSCE9.png
Figure 29. Circuit Breaker Timer Fault Assertion Delay vs Temperature
TPS25942A TPS25942L TPS25944A TPS25944L 1_TurnON_EN_4.5V Cdvdt0nF.png
V(IN) = 4.5 V
Figure 31. Turnon With Enable
TPS25942A TPS25942L TPS25944A TPS25944L 3_EN_Ramp_11OhmLoad_11VV_TON(dly).png
R(FLT) = 100 kΩ
Figure 33. EN Turnon Delay : EN ↑ to Output Ramp ↑
TPS25942A TPS25942L TPS25944A TPS25944L 5_OVP_11Ohm_Load_TOVPR(dly).png
V(IN) = 12 V RL = 12 Ω R(FLT) = 100 kΩ
Figure 35. OVP Turnoff Delay: OVP ↑ to Fault ↓
TPS25942A TPS25942L TPS25944A TPS25944L 7_Power Good Deglitch_Raising.png
V(IN) = 12 V RL = 12 Ω R(FLT) = 100 kΩ
R(PGOOD) = 100 kΩ
Figure 37. Power Good Delay (Rising)
TPS25942A TPS25942L TPS25944A TPS25944L 9_Hot_Short_Fasttrip_response_Current_Regulation.png
V(IN) = 12 V R(IMON) = 16.9 kΩ R(FLT) = 100 kΩ
R(ILIM) = 17.8 KΩ
Figure 39. Hot-Short: Fast Trip Response and Current Regulation
TPS25942A TPS25942L TPS25944A TPS25944L 11_ENLBLK-21OhmLoad_12V_Blocing FET disable(dly).png
Figure 41. Transition from Normal Mode to Non-Ideal Diode Mode
TPS25942A TPS25942L TPS25944A TPS25944L figure44_slvsce9.png
V(IN) = 12 V RL = 3 Ω to 2 Ω R(IMON) = 16.9 kΩ
R(ILIM) = 17.8 KΩ R(FLT) = 100 kΩ
Figure 43. Overload: TPS25944A Circuit Break Function
TPS25942A TPS25942L TPS25944A TPS25944L figure46_slvsce9.png
V(IN) = 5 V R(IMON) = 16.9 kΩ R(FLT) = 100 kΩ
R(ILIM) = 17.8 KΩ
Figure 45. Hot Short Response: TPS25944A
Device Turns Off after the Fault Timer tCB(dly) (4 ms) Expires
TPS25942A TPS25942L TPS25944A TPS25944L D002_SLVSCE9.gif
Figure 2. Input Supply Current vs Supply Voltage During Normal Operation
TPS25942A TPS25942L TPS25944A TPS25944L C004_SLVSCE9.png
Figure 4. EN Threshold Voltage vs Temperature
TPS25942A TPS25942L TPS25944A TPS25944L C006_SLVSCE9.png
Figure 6. PGTH Threshold Voltage vs Temperature
TPS25942A TPS25942L TPS25944A TPS25944L C008_SLVSCE9.png
Figure 8. Enable Turnon Delay vs Temperature
TPS25942A TPS25942L TPS25944A TPS25944L C100_SLVSCE9.png
Figure 10. OVP Disable Delay vs Temperature
TPS25942A TPS25942L TPS25944A TPS25944L D203_SLVSCE9.gif
Figure 12. DMODE Pulldown Current vs Temperature
TPS25942A TPS25942L TPS25944A TPS25944L C014_SLVSCE9.png
Figure 14. Output Ramp Time vs C(dVdT)
TPS25942A TPS25942L TPS25944A TPS25944L C016_SLVSCE9.png
Figure 16. Current Limit Accuracy vs Current Limit
TPS25942A TPS25942L TPS25944A TPS25944L D018_SLVSCE9.gif
Figure 18. Current Limit (% Normalized) vs Temperature
TPS25942A TPS25942L TPS25944A TPS25944L C019_SLVSCE9.png
Figure 20. Current Limit for R(ILIM) = Open and Short vs Temperature
TPS25942A TPS25942L TPS25944A TPS25944L D022_SLVSCE9.gif
Figure 22. IMON Offset vs Temperature
TPS25942A TPS25942L TPS25944A TPS25944L C024_SLVSCE9.png
Figure 24. Current Monitor Output vs Output Current
TPS25942A TPS25942L TPS25944A TPS25944L C026_SLVSCE9.png
Figure 26. OUT Leakage Current in Off State vs Temperature
TPS25942A TPS25942L TPS25944A TPS25944L C103_SLVSCE9.png
Figure 28. V(FWDTH) vs Temperature
TPS25942A TPS25942L TPS25944A TPS25944L C029_SLVSCE9.png
Taken on 2-Layer board, 2oz.(0.08-mm thick) with GND plane area: 14 cm2 (Top) and 20 cm2 (Bottom)
Figure 30. Thermal Shutdown Time vs Power Dissipation
TPS25942A TPS25942L TPS25944A TPS25944L 2_EN_Ramp_11OhmLoad_11V_IIN.png
V(IN) = 11 V
Figure 32. Turnon and Turnoff With Enable
TPS25942A TPS25942L TPS25944A TPS25944L 4_EN_Ramp_11OhmLoad_11V_TOFF(dly).png
R(FLT) = 100 kΩ
Figure 34. EN Turnoff Delay : EN ↓ to Fault ↓
TPS25942A TPS25942L TPS25944A TPS25944L 6_OVP_11Ohm_Load_TOVPF(dly).png
V(IN) = 12 V RL = 12 Ω R(FLT) = 100 kΩ
Figure 36. OVP Turnon Delay: OVP ↓ to Output Ramp ↑
TPS25942A TPS25942L TPS25944A TPS25944L 8_Power Good Deglitch_Falling.png
V(IN) = 12 V RL = 12 Ω R(FLT) = 100 kΩ
R(PGOOD) = 100 kΩ
Figure 38. Power Good Delay (Falling)
TPS25942A TPS25942L TPS25944A TPS25944L 10_Hot_Short_Fasttrip_response_Zoomed.png
V(IN) = 12 V R(IMON) = 16.9 kΩ R(FLT) = 100 kΩ
R(ILIM) = 17.8 KΩ
Figure 40. Hot-Short: Fast Trip Response (Zoomed)
TPS25942A TPS25942L TPS25944A TPS25944L 12_ENLBLK-21OhmLoad_12V_tENBLKON(dly).png
Figure 42. Transition from Non-Ideal Diode Mode to Normal Mode
TPS25942A TPS25942L TPS25944A TPS25944L figure45_slvsce9.png
Figure 44. Overload: Zoomed In (First Cycle)
TPS25942A TPS25942L TPS25944A TPS25944L figure47_slvsce9.png
V(IN) = 12 V R(IMON) = 16.9 kΩ R(FLT) = 100 kΩ
R(ILIM) = 17.8 KΩ
Figure 46. Hot Short Response: TPS25944A
Device Turns Off When TJ > T(TSD) Before Timer Expires