ZHCSCQ0 August 2014 TPS25921A , TPS25921L
PRODUCTION DATA.
The TPS25921x is a smart eFuse. It is typically used for Hot-Swap and Power rail protection applications. It operates from 4.5 V to 18 V with programmable current limit, overvoltage and undervoltage protection. The device aids in controlling the in-rush current and provides precise current limiting during overload conditions for systems such as White Goods, Set-Top-Box, DTVs, Gaming Consoles, SSDs/HDDs and Smart Meters. The device also provides robust protection for multiple faults on the sub-system rail.
The following design procedure can be used to select component values for the device.
Alternatively, the WEBENCH® software may be used to generate a complete design. The WEBENCH® software uses an iterative design procedure and accesses a comprehensive database of components when generating a design. Additionally, a spreadsheet design tool TPS25921 Design Calculator is available on web folder.
This section presents a simplified discussion of the design process.
DESIGN PARAMETER | EXAMPLE VALUE |
---|---|
Input voltage range, V_{(IN)} | 12 V |
Undervoltage lockout set point, V_{(UV)} | 8 V |
Overvoltage protection set point , V_{(OV)} | 17 V |
Load at Start-Up , R_{L(SU)} | 24 Ω |
Current limit, I_{LIMIT} | 1 A |
Load capacitance , C_{(OUT)} | 100 µF |
Maximum ambient temperatures , T_{A} | 85°C |
The following design procedure can be used to select component values for the TPS25921A and TPS25921L.
To begin the design process a few parameters must be decided upon. The designer needs to know the following:
This design procedure below seeks to control the junction temperature of device under both static and transient conditions by proper selection of output ramp-up time and associated support components. The designer can adjust this procedure to fit the application and design criteria.
The R_{(ILIM)} resistor at the ILIM pin sets the over load current limit, this can be set using Equation 5.
Choose closest standard value: 95.3 kΩ, 1% standard value resistor.
The undervoltage lockout (UVLO) and overvoltage trip point are adjusted using the external voltage divider network of R_{1}, R_{2} and R_{3} as connected between IN, ENUV, OVP and GND pins of the device. The values required for setting the undervoltage and overvoltage are calculated solving Equation 9 and Equation 10.
For minimizing the input current drawn from the power supply \{I_{(R123)} = V_{(IN)}/(R_{1} + R_{2} + R_{3})\}, it is recommended to use higher values of resistance for R_{1}, R_{2} and R_{3}.
However, leakage currents due to external active components connected to the resistor string can add error to these calculations. So, the resistor string current, I_{(R123)} must be chosen to be 20x greater than the leakage current expected.
From the device electrical specifications, V_{(OVPR)} = 1.40 V and V_{(ENR)} = 1.40 V. For design requirements, V_{(OV)} is 17 V and V_{(UV)} is 8 V. To solve the equation, first choose the value of R_{3} = 47 kΩ and use Equation 9 to solve for (R_{1} + R_{2}) = 523.71 kΩ. Use Equation 10 and value of (R_{1} + R_{2}) to solve for R_{2} = 52.88 kΩ and finally R_{1}= 470.83 kΩ.
Using the closest standard 1% resistor values gives R_{1} = 470 kΩ, R_{2} = 53 kΩ, and R_{3} = 47 kΩ.
The power failure threshold is detected on the falling edge of supply. This threshold voltage is 4% lower than the rising threshold, V_{(UV)}. This is calculated using Equation 11.
Power fail threshold set is : 7.68 V
For a successful design, the junction temperature of device should be kept below the absolute-maximum rating during both dynamic (start-up) and steady state conditions. Dynamic power stresses often are an order of magnitude greater than the static stresses, so it is important to determine the right start-up time and in-rush current limit required with system capacitance to avoid thermal shutdown during start-up with and without load.
The ramp-up capacitor C_{(SS)} needed is calculated considering the two possible cases:
During start-up, as the output capacitor charges, the voltage difference across the internal FET decreases, and the power dissipated decreases as well. Typical ramp-up of output voltage V_{(OUT)} with inrush current limit of 0.5A and power dissipated in the device during start-up is shown in Figure 31. The average power dissipated in the device during start-up is equal to area of triangular plot (red curve in Figure 32) averaged over t_{SS}.
V_{(IN)} = 12 V | C_{(SS)} = 1 nF | C_{(OUT)}=100 µF |
V_{(IN)} = 12 V | C_{(SS)} = 1 nF | C_{(OUT)}=100 µF |
For TPS25921 device, the inrush current is determined as,
Power dissipation during start-up is:
Equation 13 assumes that load does not draw any current until the output voltage has reached its final value.
When load draws current during the turn-on sequence, there will be additional power dissipated. Considering a resistive load R_{L(SU)} during start-up, load current ramps up proportionally with increase in output voltage during t_{SS} time. Typical ramp-up of output voltage, load current and power dissipation in the device is shown in Figure 33 and power dissipation with respect to time is plotted in Figure 34. The additional power dissipation during start-up phase is calculated as follows.
Where R_{L(SU)} is the load resistance present during start-up. Average energy loss in the internal FET during charging time due to resistive load is given by:
V_{(IN)} = 12 V | C_{(SS)} = 1 nF , C_{(OUT)}=100 µF | R_{L(SU)} = 24 Ω |
V_{(IN)} = 12 V | C_{(SS)} = 1 nF | R_{L(SU)} = 24 Ω |
On solving Equation 16 the average power loss in the internal FET due to load is:
Total power dissipated in the device during startup is:
Total current during startup is given by:
If I_{(STARTUP)} > I_{LIMIT}, the device limits the current to I_{LIMIT} and the current limited charging time is determined by:
The power dissipation, with and without load, for selected start-up time should not exceed the shutdown limits as shown in Figure 35.
For the design example under discussion,
Select ramp-up capacitor C_{(SS)} = 1nF, using Equation 2.
The inrush current drawn by the load capacitance (C_{(OUT)}) during ramp-up using Equation 3.
The inrush Power dissipation is calculated, using Equation 13.
For 2.72 W of power loss, the thermal shut down time of the device should not be less than the ramp-up time t_{SS} to avoid the false trip at maximum operating temperature. From thermal shutdown limit graph Figure 35 at
T_{A} = 85°C, for 2.72 W of power the shutdown time is ~170 ms. So it is safe to use 2.64 ms as start-up time without any load on output.
Considering the start-up with load 24 Ω, the additional power dissipation, when load is present during start up is calculated, using Equation 17.
The total device power dissipation during start up is:
From thermal shutdown limit graph at T_{A} = 85°C, the thermal shutdown time for 3.72 W is close to 60 ms. It is safe to have 30% margin to allow for variation of system parameters such as load, component tolerance, and input voltage. So it is well within acceptable limits to use the 1 nF capacitor with start-up load of 24 Ω.
If there is a need to decrease the power loss during start-up, it can be done with increase of C_{(SS) }capacitor.
To illustrate, choose C_{(SS)} = 4.7 nF as an option and recalculate:
From thermal shutdown limit graph at T_{A} = 85°C, the shutdown time for 1.61 W power dissipation is ~1000 ms, which increases the margins further for shutdown time and ensures successful operation during start up and steady state conditions.
The spreadsheet tool available on the web can be used for iterative calculations.
Reference to application schematics, R_{4} is required only if FLT is used; The resistor serves as pull-up for the open-drain output driver. The current sunk by this pin should not exceed 100 mA (refer to the Absolute Maximum Ratings table). C_{IN} is a bypass capacitor to help control transient voltages, unit emissions, and local supply noise. Where acceptable, a value in the range of 0.001 μF to 0.1 μF is recommended for C_{(IN)}.