ZHCSBB7C JULY   2013  – December 2014 TPL5100

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Ratings
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements TCAL, MOS_DRV, DONE, PGOOD
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Supervisor Feature
      2. 7.3.2 Calibration Pulse
        1. 7.3.2.1 Overview of the Timing Signals MOS_DRV, TCAL, and DONE
      3. 7.3.3 Configuration and Interface
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 商标
    2. 11.2 静电放电警告
    3. 11.3 术语表
  12. 12机械封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

VSSOP
10 Pins
Top View
PINOUT2.gif

Pin Functions

PIN I/O DESCRIPTION APPLICATION INFORMATION
NAME NO.
D0 1 I Logic Input to set period delay (tDP) Connect to GND (low logic value) or to VDD (high logic value)
D1 2 I Logic Input to set period delay (tDP) Connect to GND (low logic value) or to VDD (high logic value)
D2 3 I Logic Input to set period delay (tDP) Connect to GND (low logic value) or to VDD (high logic value)
VDD 4 P Supply voltage
GND 5 G Ground
DONE 6 I Logic input for Watchdog functionality
TCAL 7 O Short duration pulse output for estimation of TPL5100 timer delay.
MOS_DRV 8 O Drives external MOSFET to power cycle the remaining system.
DNC 9 – Do Not Connect Leave this pin floating
PGOOD 10 I Digital power good input