ZHCSBB7C JULY 2013 – December 2014 TPL5100
The more sensitive pins of the TPL5100 are the digital input pins D0, D1, D2 to select the timer interval. It is mandatory to connect them to VDD or GND through short traces avoiding series resistance. Moreover, it is mandatory to keep these pins far from traces of high frequency signals, such as clock or communication bus. Signal integrity of DRV and TCAL signal is achieved reducing parasitic capacitance on the traces between the TPL5100 and the microcontroller.