ZHCSCQ5C August 2014 – September 2017 TPD1E05U06-Q1 , TPD4E05U06-Q1
PRODUCTION DATA.
TPDxE05U06-Q1 是一系列具有超低电容的单向瞬态电压抑制器 (TVS) 静电放电 (ESD) 保护二极管。这些器件旨在耗散那些高于 IEC61000-4-2 4 级国际标准中规定的最高水平的 ESD 冲击。超低负载电容特性使得这些器件非常适合保护任何高达 6Gbps 的高速 信号 应用。
这些器件还具有未经过汽车认证的型号:TPDxE05U06。
器件型号 | 封装 | 封装尺寸(标称值) |
---|---|---|
TPD4E05U06-Q1 | USON (10) | 2.50mm x 1.00mm |
TPD1E05U06-Q1 | X1SON (2) | 0.60mm x 1.00mm |
Changes from A Revision (August 2014) to B Revision
Changes from B Revision (August 2016) to C Revision
Changes from * Revision (August 2014) to A Revision
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | I/O | I/O | ESD Protected Channel(1) |
2 | GND | Ground | Ground; Connect to ground |
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | D1+ | I/O | ESD Protected Channel(1) |
2 | D1– | I/O | ESD Protected Channel(1) |
4 | D2+ | I/O | ESD Protected Channel(1) |
5 | D2– | I/O | ESD Protected Channel(1) |
6, 7, 9, 10 | NC | NC | Not Connected; Used for optional straight-through routing. Can be left floating or grounded |
3, 8 | GND | Ground | Ground; Connect to ground |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Electrical fast transient | IEC 61000-4-4 (5/50 ns) | 80 | A | |
Peak pulse | IEC 61000-4-5 Current (tp – 8/20 µs) | 2.5 | A | |
IEC 61000-4-5 Power (tp – 8/20 µs) - TPD4E05U06-Q1(3) | 40 | W | ||
IEC 61000-4-5 Power (tp – 8/20 µs) - TPD1E05U06-Q1(3) | 30 | W | ||
TA | Operating temperature | –40 | 125 | °C |
Tstg | Storage temperature | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge(1) | Human-body model (HBM), per AEC Q100-002(2) | ±8000 | V |
Charged-device model (CDM), per AEC Q100-011 | ±1000 |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic Discharge | IEC 61000-4-2 contact discharge - TPD4E05U06-Q1 (1) | ±12000 | V |
IEC 61000-4-2 contact discharge - TPD1E05U06-Q1 | ±12000 | |||
IEC 61000-4-2 air-gap discharge | ±15000 |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VIO | Input pin voltage | 0 | 5.5 | V |
TA | Operating free-air temperature | –40 | 125 | °C |
THERMAL METRIC(1) | TPD1E05U06-Q1 | TPD4E05U06-Q1 | UNIT | |
---|---|---|---|---|
DPY (X1SON) | DQA (USON) | |||
2 PINS | 10 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 697.3 | 327 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 471 | 189.5 | °C/W |
RθJB | Junction-to-board thermal resistance | 575.9 | 257.7 | °C/W |
ψJT | Junction-to-top characterization parameter | 175.7 | 60.9 | °C/W |
ψJB | Junction-to-board characterization parameter | 575.1 | 257 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|---|---|
INPUT – OUTPUT RESISTANCE | ||||||||
VRWM | Reverse stand-off voltage | IIO < 10 µA | 5.5 | V | ||||
VBR | Break-down voltage | IIO = 1 mA | 6.4 | 8.7 | V | |||
VCLAMP | Clamp voltage | IPP = 1 A, TLP, from I/O to GND(1) | 10 | V | ||||
IPP = 5 A, TLP, from I/O to GND(1) | 14 | |||||||
IPP = 1 A, TLP, from GND to I/O(1) | 3 | |||||||
IPP = 5 A, TLP, from GND to I/O(1) | 7.5 | |||||||
ILEAK | Leakage current | VIO = 2.5 V | 1 | 10 | nA | |||
RDYN | Dynamic resistance | DPY package | I/O to GND(2) | 0.8 | Ω | |||
GND to I/O(2) | 0.7 | |||||||
DQA package | I/O to GND(2) | 0.96 | ||||||
GND to I/O(2) | 0.9 | |||||||
CAPACITANCE | ||||||||
CL | Line capacitance | VIO = 2.5 V, f = 1 MHz, I/O to GND | TPD1E05U06-Q1 DPY package | 0.42 | pF | |||
TPD4E05U06-Q1 DQA package | 0.5 | |||||||
Δ CIO-TO-GND | Variation of input capacitance | GND Pin = 0 V, f = 1 MHz, VBIAS = 2.5 V, Channel x pin to GND – channel y pin to GND |
0.05 | 0.08 | pF | |||
CCROSS | Channel to channel input capacitance | GND Pin = 0 V, f = 1 MHz, VBIAS = 2.5 V, between channel pins | 0.04 | 0.08 | pF |
The TPDxE05U06-Q1 is a family of unidirectional TVS ESD protection diode arrays with ultra-low capacitance between 0.42 pF and 0.5 pF. They are rated to dissipate ESD strikes above the maximum level specified in the IEC 61000-4-2 level 4 international standard (12-kV contact, 15-kV air gap). The ultra-low loading capacitance makes them ideal for protecting any high-speed signal applications up to 6 Gbps.
These devices are qualified to AEC-Q101 standards. They pass HBM H3B (±8 kV) and CDM C5 (±1 kV) ESD ratings and are qualified to operate from –40°C to +125°C.
The I/O pins can withstand ESD events up to ±12-kV contact and ±15-kV air. An ESD-surge clamp diverts the current to ground.
The I/O pins can withstand an electrical fast transient burst of up to 80 A (5/50 ns waveform, 4 kV with 50-Ω impedance). An ESD-surge clamp diverts the current to ground.
The I/O pins can withstand surge events up to 2.5 A and 40 W (8/20 µs waveform). An ESD-surge clamp diverts this current to ground.
The capacitance between each I/O pin to ground is 0.5 pF. These capacitances support data rates up to 5 Gbps.
The DC breakdown voltage of each I/O pin is a minimum of 6.4 V. This ensures that sensitive equipment is protected from surges above the reverse standoff voltage of 5 V.
The I/O pins feature an ultra-low leakage current of 10 nA (Maximum) with a bias of 2.5 V.
The I/O pins feature an ESD clamp that is capable of clamping the voltage to 10 V (IPP = 1 A).
The layout of this device makes it simple and easy to add protection to an existing layout. The packages offers flow-through routing, requiring minimal modification to an existing layout.
The TPDxE05U06-Q1 are passive integrated circuits that triggers when voltages are above VBR or below the lower diodes Vf (–0.6 V). During ESD events, voltages as high as ±15 kV (air) can be directed to ground via the internal diode network. When the voltages on the protected line fall below the trigger levels of TPDxE05U06-Q1 (usually within 10s of nano-seconds) the devices reverts to passive.
The TPD4E05U06-Q1 is a diode type TVS which is typically used to provide a path to ground for dissipating ESD events on hi-speed signal lines between a human interface connector and a system. As the current from ESD passes through the TVS, only a small voltage drop is present across the diode. This is the voltage presented to the protected IC. The low RDYN of the triggered TVS holds this voltage, VCLAMP, to a safe level for the protected IC.
For this design example, two TPD4E05U06-Q1 devices, and a TPD5S116 are being used in an HDMI 1.4 application. This provides a complete port protection scheme.
Given the HDMI 1.4 application, the parameters in Table 1 are known.
DESIGN PARAMETER | VALUE |
---|---|
Signal range on pins 1, 2, 4, or 5 | 0 V to 5 V |
Operating frequency | 1.7 GHz |
To begin the design process, some parameters must be decided upon; the designer needs to know the following:
The TPD4E05U06-Q1 has 4 identical protection channels for signal lines. The symmetry of the device provides flexibility when selecting which of the 4 I/O channels protect which signal lines. Any I/O will support a signal range of 0 to 5.5 V.
The TPD4E05U06-Q1 has a capacitance of 0.5 pF (Typical), supporting HDMI 1.4 data rates.
This application is typical of an HDMI 1.4 layout.
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ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可能会导致器件与其发布的规格不相符。
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