SLOS524E June   2008  – May 2016 TPA2016D2

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C Timing Requirements
    7. 7.7 Dissipation Ratings
    8. 7.8 Operating Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Operation With DACs and CODECs
      2. 9.3.2 Filter-Free Operation and Ferrite Bead Filters
      3. 9.3.3 Short-Circuit Protection
      4. 9.3.4 Automatic Gain Control
        1. 9.3.4.1 Fixed Gain
        2. 9.3.4.2 Limiter Level
        3. 9.3.4.3 Compression Ratio
        4. 9.3.4.4 Interaction Between Compression Ratio and Limiter Range
        5. 9.3.4.5 Noise Gate Threshold
        6. 9.3.4.6 Maximum Gain
        7. 9.3.4.7 Attack, Release, and Hold Time
    4. 9.4 Device Functional Modes
      1. 9.4.1 TPA2016D2 AGC Operation
      2. 9.4.2 TPA2016D2 AGC Recommended Settings
    5. 9.5 Programming
      1. 9.5.1 General I2C Operation
      2. 9.5.2 Single- and Multiple-Byte Transfers
      3. 9.5.3 Single-Byte Write
      4. 9.5.4 Multiple-Byte Write and Incremental Multiple-Byte Write
      5. 9.5.5 Single-Byte Read
      6. 9.5.6 Multiple-Byte Read
    6. 9.6 Register Maps
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 TPA2016D2 With Differential Input Signal
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Surface Mount Capacitors
          2. 10.2.1.2.2 Decoupling Capacitor, CS
          3. 10.2.1.2.3 Input Capacitors, CI
        3. 10.2.1.3 Application Curves
      2. 10.2.2 TPA2016D2 With Single-Ended Input Signal
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Power Supply Decoupling Capacitors
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Component Location
      2. 12.1.2 Trace Width
      3. 12.1.3 Pad Side
    2. 12.2 Layout Examples
    3. 12.3 Efficiency and Thermal Considerations
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

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订购信息

6 Pin Configuration and Functions

YZH Package
16-Pin DSBGA
Top View
RTJ Package
20-Pin QFN
Top View

Pin Functions

PIN TYPE DESCRIPTION
NAME DSBGA QFN
INR+ A2 15 I Right channel positive audio input
INR– A1 14 I Right channel negative audio input
INL+ A3 1 I Left channel positive audio input
INL– A4 2 I Left channel negative audio input
SDZ C2 18 I Shutdown terminal (active low)
SDA B3 19 I/O I2C data interface
SCL B2 17 I I2C clock interface
OUTR+ D1 10 O Right channel positive differential output
OUTR– D2 9 O Right channel negative differential output
OUTL+ D4 6 O Left channel positive differential output
OUTL– D3 7 O Left channel negative differential output
AVDD B1 13 P Analog supply (must be the same as PVDDR and PVDDL)
AGND B4 3 P Analog ground (all GND pins need to be connected)
PVDDR C1 11, 12 P Right channel power supply (must be the same as AVDD and PVDDL)
PGND C3 8 P Power ground (all GND pins need to be connected)
PVDDL C4 4, 5 P Left channel power supply (must be the same as AVDD and PVDDR)