SLOS438F December   2004  – March 2017 TPA2012D2

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Dissipation Rating Table
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Fixed Gain Setting
      2. 9.3.2 Short-Circuit Protection
      3. 9.3.3 Operation With DACs and CODECs
      4. 9.3.4 Filter-Free Operation and Ferrite Bead Filters
    4. 9.4 Device Functional Modes
      1. 9.4.1 Shutdown Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 TPA2012D2 With Differential Input Signal
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Surface Mount Capacitors
          2. 10.2.1.2.2 Decoupling Capacitor (CS)
          3. 10.2.1.2.3 Input Capacitors (CI)
        3. 10.2.1.3 Application Curves
      2. 10.2.2 TPA2012D2 With Single-Ended Input Signal
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Power Supply Decoupling Capacitor
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Pad Side
      2. 12.1.2 Component Location
      3. 12.1.3 Trace Width
    2. 12.2 Layout Examples
    3. 12.3 Efficiency and Thermal Considerations
  13. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

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12 Layout

12.1 Layout Guidelines

12.1.1 Pad Side

In making the pad size for the DSBGA balls, TI recommends that the layout use non-solder mask defined (NSMD) land. With this method, the solder mask opening is made larger than the desired land area, and the opening size is defined by the copper pad width. Figure 39 and Table 5 shows the appropriate diameters for a DSBGA layout. The TPA2012D2 evaluation module (EVM) layout is shown in the next section as a layout example.

Table 5. Land Pattern Dimensions(1)(3)(2)(4)

SOLDER PAD
DEFINITIONS		 COPPER
PAD		 SOLDER MASK(5)
OPENING		 COPPER
THICKNESS		 STENCIL(6)(7)
OPENING		 STENCIL
THICKNESS
Nonsolder mask defined (NSMD) 275 µm
(+0.0, –25 µm)		 375 µm (+0.0, –25 µm) 1 oz max (32 µm) 275 µm × 275 µm (square)
(rounded corners)		 125 µm
(1) Circuit traces from NSMD defined PWB lands should be 75 µm to 100 µm wide in the exposed area inside the solder mask opening. Wider trace widths reduce device stand off and impact reliability.
(2) Recommend solder paste is Type 3 or Type 4.
(3) Best reliability results are achieved when the PWB laminate glass transition temperature is above the operating the range of the intended application.
(4) For a PWB using a Ni/Au surface finish, the gold thickness should be less 0.5 mm to avoid a reduction in thermal fatigue performance.
(5) Solder mask thickness should be less than 20 µm on top of the copper circuit pattern
(6) Best solder stencil performance is achieved using laser cut stencils with electro polishing. Use of chemically etched stencils results in inferior solder paste volume control.
(7) Trace routing away from DSBGA device should be balanced in X and Y directions to avoid unintentional component movement due to solder wetting forces.
TPA2012D2 land_pattern_los438.gif Figure 39. Land Pattern Dimensions

12.1.2 Component Location

Place all the external components very close to the TPA2012D2. Placing the decoupling capacitor, CS, close to the TPA2012D2 is important for the efficiency of the Class-D amplifier. Any resistance or inductance in the trace between the device and the capacitor can cause a loss in efficiency.

12.1.3 Trace Width

Recommended trace width at the solder balls is 75 µm to 100 µm to prevent solder wicking onto wider PCB traces.

For high current pins (PVDD, PGND, and audio output pins) of the TPA2012D2, use 100-µm trace widths at the solder balls and at least 500-µm PCB traces to ensure proper performance and output power for the device.

For the remaining signals of the TPA2012D2, use 75-µm to 100-µm trace widths at the solder balls. The audio input pins (INR± and INL±) must run side-by-side to maximize common-mode noise cancellation.

12.2 Layout Examples

TPA2012D2 TPA2012D2DSBGA.gif Figure 40. TPA2012D2 DSBGA Layout Example
TPA2012D2 TPA2012D2QFN_v2.gif Figure 41. TPA2012D2 WQFN Layout Example

12.3 Efficiency and Thermal Considerations

The maximum ambient temperature depends on the heat-sinking ability of the PCB system. The derating factor for the packages are shown in the dissipation rating table. Converting this to θJA for the WQFN package with Equation 3.

Equation 3. TPA2012D2 q_theta_ja_los438.gif

Given θJA of 24°C/W, the maximum allowable junction temperature of 150°C, and the maximum internal dissipation of 1.5 W (0.75 W per channel) for 2.1 W per channel, 4-Ω load, 5-V supply, from Figure 25, the maximum ambient temperature can be calculated with Equation 4.

Equation 4. TPA2012D2 q_tamax_los438.gif

Equation 4 shows that the calculated maximum ambient temperature is 114°C at maximum power dissipation with a 5-V supply and a 4-Ω load. The TPA2012D2 is designed with thermal protection that turns the device off when the junction temperature surpasses 150°C to prevent damage to the IC. Also, using speakers more resistive than 4-Ω dramatically increases the thermal performance by reducing the output current and increasing the efficiency of the amplifier.