ZHCSM12D September   2020  – August 2022 TMUX6219

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Thermal Information
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Source or Drain Continuous Current
    6. 6.6  ±15 V Dual Supply: Electrical Characteristics 
    7. 6.7  ±15 V Dual Supply: Switching Characteristics 
    8. 6.8  36 V Single Supply: Electrical Characteristics 
    9. 6.9  36 V Single Supply: Switching Characteristics 
    10. 6.10 12 V Single Supply: Electrical Characteristics 
    11. 6.11 12 V Single Supply: Switching Characteristics 
    12. 6.12 +5 V / -8 V Dual Supply: Electrical Characteristics 
    13. 6.13 +5 V / -8 V Dual Supply: Switching Characteristics 
    14. 6.14 ±5 V Dual Supply: Electrical Characteristics 
    15. 6.15 ±5 V Dual Supply: Switching Characteristics 
    16. 6.16 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1  On-Resistance
    2. 7.2  Off-Leakage Current
    3. 7.3  On-Leakage Current
    4. 7.4  Transition Time
    5. 7.5  tON(EN) and tOFF(EN)
    6. 7.6  Break-Before-Make
    7. 7.7  tON (VDD) Time
    8. 7.8  Propagation Delay
    9. 7.9  Charge Injection
    10. 7.10 Off Isolation
    11. 7.11 Crosstalk
    12. 7.12 Bandwidth
    13. 7.13 THD + Noise
    14. 7.14 Power Supply Rejection Ratio (PSRR)
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Bidirectional Operation
      2. 8.3.2 Rail to Rail Operation
      3. 8.3.3 1.8 V Logic Compatible Inputs
      4. 8.3.4 Fail-Safe Logic
      5. 8.3.5 Latch-Up Immune
      6. 8.3.6 Ultra-Low Charge Injection
    4. 8.4 Device Functional Modes
    5. 8.5 Truth Tables
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Power Amplifier Gate Driver
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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8.3.6 Ultra-Low Charge Injection

The TMUX6219 has a transmission gate topology, as shown in Figure 8-2. Any mismatch in the stray capacitance associated with the NMOS and PMOS causes an output level change whenever the switch is opened or closed.

GUID-E509C7FD-0F79-4AD4-9FE9-87F07F01D1E9-low.gif Figure 8-2 Transmission Gate Topology

The TMUX6219 contains specialized architecture to reduce charge injection on the source (Sx). To further reduce charge injection in a sensitive application, a compensation capacitor (Cp) can be added on the drain (D). This will ensure that excess charge from the switch transition will be pushed into the compensation capacitor on the drain (D) instead of the source (Sx). As a general rule, Cp should be 20× larger than the equivalent load capacitance on the source (Sx). Figure 8-3 shows charge injection variation with source voltage with different compensation capacitors on the Drain side.

Figure 8-3 Charge Injection Compensation