ZHCSJM4A April   2019  – October 2019 TMUX1204

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      应用示例
      2.      TMUX1204 方框图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics (VDD = 5 V ±10 %)
    6. 6.6 Electrical Characteristics (VDD = 3.3 V ±10 %)
    7. 6.7 Electrical Characteristics (VDD = 1.8 V ±10 %)
    8. 6.8 Electrical Characteristics (VDD = 1.2 V ±10 %)
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1  On-Resistance
    2. 7.2  Off-Leakage Current
    3. 7.3  On-Leakage Current
    4. 7.4  Transition Time
    5. 7.5  Break-Before-Make
    6. 7.6  tON(EN) and tOFF(EN)
    7. 7.7  Charge Injection
    8. 7.8  Off Isolation
    9. 7.9  Crosstalk
    10. 7.10 Bandwidth
  8. 8 Detailed Description
    1. 8.1 Functional Block Diagram
    2. 8.2 Feature Description
      1. 8.2.1 Bidirectional Operation
      2. 8.2.2 Rail to Rail Operation
      3. 8.2.3 1.8 V Logic Compatible Inputs
      4. 8.2.4 Fail-Safe Logic
    3. 8.3 Device Functional Modes
    4. 8.4 Truth Tables
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
    3. 9.3 Design Requirements
    4. 9.4 Detailed Design Procedure
    5. 9.5 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Layout Information
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档
    2. 12.2 接收文档更新通知
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

DGS Package
10-Pin VSSOP
Top View
DQA Package
10-Pin USON
Top View

Pin Functions

PIN TYPE(1) DESCRIPTION(2)
NAME DGS, DQA
A0 1 I Address line 0. Controls the switch configuration as shown in Table 1.
S1 2 I/O Source pin 1. Can be an input or output.
GND 3 P Ground (0 V) reference
S3 4 I/O Source pin 3. Can be an input or output.
EN 5 I Active high logic enable. When this pin is low, all switches are turned off. When this pin is high, the A[1:0] logic inputs determine which switch is turned on.
VDD 6 P Positive power supply. This pin is the most positive power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
S4 7 I/O Source pin 4. Can be an input or output.
D 8 I/O Drain pin. Can be an input or output.
S2 9 I/O Source pin 2. Can be an input or output.
A1 10 I Address line 1. Controls the switch configuration as shown in Table 1.
(1) I = input, O = output, I/O = input and output, P = power
(2) For unused pins, refer to the Device Functional Modes