SPNS253A May   2018  – September 2019 TMS570LC4357-EP

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2 Revision History
  3. 3 Terminal Configuration and Functions
    1. 3.1 GWT BGA Package Ball-Map (337 Terminal Grid Array)
    2. 3.2 Terminal Functions
      1. 3.2.1 GWT Package
        1. 3.2.1.1  Multibuffered Analog-to-Digital Converters (MibADC)
        2. 3.2.1.2  Enhanced High-End Timer Modules (N2HET)
        3. 3.2.1.3  RAM Trace Port (RTP)
        4. 3.2.1.4  Enhanced Capture Modules (eCAP)
        5. 3.2.1.5  Enhanced Quadrature Encoder Pulse Modules (eQEP)
        6. 3.2.1.6  Enhanced Pulse-Width Modulator Modules (ePWM)
        7. 3.2.1.7  Data Modification Module (DMM)
        8. 3.2.1.8  General-Purpose Input / Output (GIO)
        9. 3.2.1.9  FlexRay Interface Controller (FlexRay)
        10. 3.2.1.10 Controller Area Network Controllers (DCAN)
        11. 3.2.1.11 Local Interconnect Network Interface Module (LIN)
        12. 3.2.1.12 Standard Serial Communication Interface (SCI)
        13. 3.2.1.13 Inter-Integrated Circuit Interface Module (I2C)
        14. 3.2.1.14 Multibuffered Serial Peripheral Interface Modules (MibSPI)
        15. 3.2.1.15 Ethernet Controller
        16. 3.2.1.16 External Memory Interface (EMIF)
        17. 3.2.1.17 Embedded Trace Macrocell Interface for Cortex-R5F (ETM-R5)
        18. 3.2.1.18 System Module Interface
        19. 3.2.1.19 Clock Inputs and Outputs
        20. 3.2.1.20 Test and Debug Modules Interface
        21. 3.2.1.21 Flash Supply and Test Pads
        22. 3.2.1.22 Supply for Core Logic: 1.2-V Nominal
        23. 3.2.1.23 Supply for I/O Cells: 3.3-V Nominal
        24. 3.2.1.24 Ground Reference for All Supplies Except VCCAD
        25. 3.2.1.25 Other Supplies
      2. 3.2.2 Multiplexing
        1. 3.2.2.1 Output Multiplexing
          1. 3.2.2.1.1 Notes on Output Multiplexing
        2. 3.2.2.2 Input Multiplexing
          1. 3.2.2.2.1 Notes on Input Multiplexing
          2. 3.2.2.2.2 General Rules for Multiplexing Control Registers
  4. 4 Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Power-On Hours (POH)
    4. 4.4  Recommended Operating Conditions
    5. 4.5  Switching Characteristics Over Recommended Operating Conditions for Clock Domains
    6. 4.6  Wait States Required - L2 Memories
    7. 4.7  Power Consumption Summary
    8. 4.8  Input/Output Electrical Characteristics Over Recommended Operating Conditions
    9. 4.9  Thermal Resistance Characteristics for the BGA Package (GWT)
    10. 4.10 Timing and Switching Characteristics
      1. 4.10.1 Input Timings
      2. 4.10.2 Output Timings
  5. 5 System Information and Electrical Specifications
    1. 5.1  Device Power Domains
    2. 5.2  Voltage Monitor Characteristics
      1. 5.2.1 Important Considerations
      2. 5.2.2 Voltage Monitor Operation
      3. 5.2.3 Supply Filtering
    3. 5.3  Power Sequencing and Power-On Reset
      1. 5.3.1 Power-Up Sequence
      2. 5.3.2 Power-Down Sequence
      3. 5.3.3 Power-On Reset: nPORRST
        1. 5.3.3.1 nPORRST Electrical and Timing Requirements
    4. 5.4  Warm Reset (nRST)
      1. 5.4.1 Causes of Warm Reset
      2. 5.4.2 nRST Timing Requirements
    5. 5.5  ARM Cortex-R5F CPU Information
      1. 5.5.1 Summary of ARM Cortex-R5F CPU Features
      2. 5.5.2 Dual Core Implementation
      3. 5.5.3 Duplicate Clock Tree After GCLK
      4. 5.5.4 ARM Cortex-R5F CPU Compare Module (CCM) for Safety
        1. 5.5.4.1 Signal Compare Operating Modes
          1. 5.5.4.1.1 Active Compare Lockstep Mode
          2. 5.5.4.1.2 Self-Test Mode
          3. 5.5.4.1.3 Error Forcing Mode
          4. 5.5.4.1.4 Self-Test Error Forcing Mode
        2. 5.5.4.2 Bus Inactivity Monitor
        3. 5.5.4.3 CPU Registers Initialization
      5. 5.5.5 CPU Self-Test
        1. 5.5.5.1 Application Sequence for CPU Self-Test
        2. 5.5.5.2 CPU Self-Test Clock Configuration
        3. 5.5.5.3 CPU Self-Test Coverage
      6. 5.5.6 N2HET STC / LBIST Self-Test Coverage
    6. 5.6  Clocks
      1. 5.6.1 Clock Sources
        1. 5.6.1.1 Main Oscillator
          1. 5.6.1.1.1 Timing Requirements for Main Oscillator
        2. 5.6.1.2 Low-Power Oscillator
          1. 5.6.1.2.1 Features
          2. 5.6.1.2.2 LPO Electrical and Timing Specifications
        3. 5.6.1.3 Phase-Locked Loop (PLL) Clock Modules
          1. 5.6.1.3.1 Block Diagram
          2. 5.6.1.3.2 PLL Timing Specifications
        4. 5.6.1.4 External Clock Inputs
      2. 5.6.2 Clock Domains
        1. 5.6.2.1 Clock Domain Descriptions
        2. 5.6.2.2 Mapping of Clock Domains to Device Modules
      3. 5.6.3 Special Clock Source Selection Scheme for VCLKA4_DIVR_EMAC
      4. 5.6.4 Clock Test Mode
    7. 5.7  Clock Monitoring
      1. 5.7.1 Clock Monitor Timings
      2. 5.7.2 External Clock (ECLK) Output Functionality
      3. 5.7.3 Dual Clock Comparators
        1. 5.7.3.1 Features
        2. 5.7.3.2 Mapping of DCC Clock Source Inputs
    8. 5.8  Glitch Filters
    9. 5.9  Device Memory Map
      1. 5.9.1 Memory Map Diagram
      2. 5.9.2 Memory Map Table
      3. 5.9.3 Special Consideration for CPU Access Errors Resulting in Imprecise Aborts
      4. 5.9.4 Master/Slave Access Privileges
        1. 5.9.4.1 Special Notes on Accesses to Certain Slaves
      5. 5.9.5 MasterID to PCRx
      6. 5.9.6 CPU Interconnect Subsystem SDC MMR Port
      7. 5.9.7 Parameter Overlay Module (POM) Considerations
    10. 5.10 Flash Memory
      1. 5.10.1 Flash Memory Configuration
      2. 5.10.2 Main Features of Flash Module
      3. 5.10.3 ECC Protection for Flash Accesses
      4. 5.10.4 Flash Access Speeds
      5. 5.10.5 Flash Program and Erase Timings
        1. 5.10.5.1 Flash Program and Erase Timings for Program Flash
        2. 5.10.5.2 Flash Program and Erase Timings for Data Flash
    11. 5.11 L2RAMW (Level 2 RAM Interface Module)
      1. 5.11.1 L2 SRAM Initialization
    12. 5.12 ECC / Parity Protection for Accesses to Peripheral RAMs
    13. 5.13 On-Chip SRAM Initialization and Testing
      1. 5.13.1 On-Chip SRAM Self-Test Using PBIST
        1. 5.13.1.1 Features
        2. 5.13.1.2 PBIST RAM Groups
      2. 5.13.2 On-Chip SRAM Auto Initialization
    14. 5.14 External Memory Interface (EMIF)
      1. 5.14.1 Features
      2. 5.14.2 Electrical and Timing Specifications
        1. 5.14.2.1 Read Timing (Asynchronous RAM)
        2. 5.14.2.2 Write Timing (Asynchronous RAM)
        3. 5.14.2.3 EMIF Asynchronous Memory Timing
        4. 5.14.2.4 Read Timing (Synchronous RAM)
        5. 5.14.2.5 Write Timing (Synchronous RAM)
        6. 5.14.2.6 EMIF Synchronous Memory Timing
    15. 5.15 Vectored Interrupt Manager
      1. 5.15.1 VIM Features
      2. 5.15.2 Interrupt Generation
      3. 5.15.3 Interrupt Request Assignments
    16. 5.16 ECC Error Event Monitoring and Profiling
      1. 5.16.1 EPC Module Operation
        1. 5.16.1.1 Correctable Error Handling
        2. 5.16.1.2 Uncorrectable Error Handling
    17. 5.17 DMA Controller
      1. 5.17.1 DMA Features
      2. 5.17.2 DMA Transfer Port Assignment
      3. 5.17.3 Default DMA Request Map
      4. 5.17.4 Using a GIO terminal as a DMA Request Input
    18. 5.18 Real-Time Interrupt Module
      1. 5.18.1 Features
      2. 5.18.2 Block Diagrams
      3. 5.18.3 Clock Source Options
      4. 5.18.4 Network Time Synchronization Inputs
    19. 5.19 Error Signaling Module
      1. 5.19.1 ESM Features
      2. 5.19.2 ESM Channel Assignments
    20. 5.20 Reset / Abort / Error Sources
    21. 5.21 Digital Windowed Watchdog
    22. 5.22 Debug Subsystem
      1. 5.22.1  Block Diagram
      2. 5.22.2  Debug Components Memory Map
      3. 5.22.3  Embedded Cross Trigger
      4. 5.22.4  JTAG Identification Code
      5. 5.22.5  Debug ROM
      6. 5.22.6  JTAG Scan Interface Timings
      7. 5.22.7  Advanced JTAG Security Module
      8. 5.22.8  Embedded Trace Macrocell (ETM-R5)
        1. 5.22.8.1 ETM TRACECLKIN Selection
        2. 5.22.8.2 Timing Specifications
      9. 5.22.9  RAM Trace Port (RTP)
        1. 5.22.9.1 RTP Features
        2. 5.22.9.2 Timing Specifications
      10. 5.22.10 Data Modification Module (DMM)
        1. 5.22.10.1 DMM Features
        2. 5.22.10.2 Timing Specifications
      11. 5.22.11 Boundary Scan Chain
  6. 6 Peripheral Information and Electrical Specifications
    1. 6.1  Enhanced Translator PWM Modules (ePWM)
      1. 6.1.1 ePWM Clocking and Reset
      2. 6.1.2 Synchronization of ePWMx Time-Base Counters
      3. 6.1.3 Synchronizing all ePWM Modules to the N2HET1 Module Time Base
      4. 6.1.4 Phase-Locking the Time-Base Clocks of Multiple ePWM Modules
      5. 6.1.5 ePWM Synchronization with External Devices
      6. 6.1.6 ePWM Trip Zones
        1. 6.1.6.1 Trip Zones TZ1n, TZ2n, TZ3n
        2. 6.1.6.2 Trip Zone TZ4n
        3. 6.1.6.3 Trip Zone TZ5n
        4. 6.1.6.4 Trip Zone TZ6n
      7. 6.1.7 Triggering of ADC Start of Conversion Using ePWMx SOCA and SOCB Outputs
      8. 6.1.8 Enhanced Translator-Pulse Width Modulator (ePWMx) Electrical Data/Timing
    2. 6.2  Enhanced Capture Modules (eCAP)
      1. 6.2.1 Clock Enable Control for eCAPx Modules
      2. 6.2.2 PWM Output Capability of eCAPx
      3. 6.2.3 Input Connection to eCAPx Modules
      4. 6.2.4 Enhanced Capture Module (eCAP) Electrical Data/Timing
    3. 6.3  Enhanced Quadrature Encoder (eQEP)
      1. 6.3.1 Clock Enable Control for eQEPx Modules
      2. 6.3.2 Using eQEPx Phase Error to Trip ePWMx Outputs
      3. 6.3.3 Input Connection to eQEPx Modules
      4. 6.3.4 Enhanced Quadrature Encoder Pulse (eQEPx) Timing
    4. 6.4  12-bit Multibuffered Analog-to-Digital Converter (MibADC)
      1. 6.4.1 MibADC Features
      2. 6.4.2 Event Trigger Options
        1. 6.4.2.1 MibADC1 Event Trigger Hookup
        2. 6.4.2.2 MibADC2 Event Trigger Hookup
        3. 6.4.2.3 Controlling ADC1 and ADC2 Event Trigger Options Using SOC Output from ePWM Modules
      3. 6.4.3 ADC Electrical and Timing Specifications
      4. 6.4.4 Performance (Accuracy) Specifications
        1. 6.4.4.1 MibADC Nonlinearity Errors
        2. 6.4.4.2 MibADC Total Error
    5. 6.5  General-Purpose Input/Output
      1. 6.5.1 Features
    6. 6.6  Enhanced High-End Timer (N2HET)
      1. 6.6.1 Features
      2. 6.6.2 N2HET RAM Organization
      3. 6.6.3 Input Timing Specifications
      4. 6.6.4 N2HET1-N2HET2 Interconnections
      5. 6.6.5 N2HET Checking
        1. 6.6.5.1 Internal Monitoring
        2. 6.6.5.2 Output Monitoring using Dual Clock Comparator (DCC)
      6. 6.6.6 Disabling N2HET Outputs
      7. 6.6.7 High-End Timer Transfer Unit (HET-TU)
        1. 6.6.7.1 Features
        2. 6.6.7.2 Trigger Connections
    7. 6.7  FlexRay Interface
      1. 6.7.1 Features
      2. 6.7.2 Electrical and Timing Specifications
      3. 6.7.3 FlexRay Transfer Unit
    8. 6.8  Controller Area Network (DCAN)
      1. 6.8.1 Features
      2. 6.8.2 Electrical and Timing Specifications
    9. 6.9  Local Interconnect Network Interface (LIN)
      1. 6.9.1 LIN Features
    10. 6.10 Serial Communication Interface (SCI)
      1. 6.10.1 Features
    11. 6.11 Inter-Integrated Circuit (I2C)
      1. 6.11.1 Features
      2. 6.11.2 I2C I/O Timing Specifications
    12. 6.12 Multibuffered / Standard Serial Peripheral Interface
      1. 6.12.1 Features
      2. 6.12.2 MibSPI Transmit and Receive RAM Organization
      3. 6.12.3 MibSPI Transmit Trigger Events
        1. 6.12.3.1 MIBSPI1 Event Trigger Hookup
        2. 6.12.3.2 MIBSPI2 Event Trigger Hookup
        3. 6.12.3.3 MIBSPI3 Event Trigger Hookup
        4. 6.12.3.4 MIBSPI4 Event Trigger Hookup
        5. 6.12.3.5 MIBSPI5 Event Trigger Hookup
      4. 6.12.4 MibSPI/SPI Master Mode I/O Timing Specifications
      5. 6.12.5 SPI Slave Mode I/O Timings
    13. 6.13 Ethernet Media Access Controller
      1. 6.13.1 Ethernet MII Electrical and Timing Specifications
      2. 6.13.2 Ethernet RMII Electrical and Timing Specifications
      3. 6.13.3 Management Data Input/Output (MDIO)
  7. 7 Applications, Implementation, and Layout
    1. 7.1 TI Design or Reference Design
  8. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
      2. 8.1.2 Device and Development-Support Tool Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation from Texas Instruments
      2. 8.2.2 Receiving Notification of Documentation Updates
      3. 8.2.3 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
    6. 8.6 Device Identification
      1. 8.6.1 Device Identification Code Register
        1. Table 8-1 Device ID Bit Allocation Register Field Descriptions
      2. 8.6.2 Die Identification Registers
    7. 8.7 Module Certifications
      1. 8.7.1 FlexRay Certifications
      2. 8.7.2 DCAN Certification
      3. 8.7.3 LIN Certification
        1. 8.7.3.1 LIN Master Mode
        2. 8.7.3.2 LIN Slave Mode - Fixed Baud Rate
        3. 8.7.3.3 LIN Slave Mode - Adaptive Baud Rate
  9. 9 Mechanical Data
    1. 9.1 Packaging Information
  10. 10Package Option Addendum
    1. 10.1 Packaging Information

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5.9.2 Memory Map Table

Table 5-25 Module Registers / Memories Memory Map

TARGET NAME MEMORY
SELECT		 ADDRESS RANGE FRAME
SIZE 		ACTUAL
SIZE		 RESPONSE FOR
ACCESS TO
UNIMPLEMENTED
LOCATIONS IN
FRAME
START END
Level 2 Memories
Level 2 Flash Data Space 0x0000_0000 0x003F_FFFF 4MB 4MB Abort
Level 2 RAM 0x0800_0000 0x083F_FFFF 4MB 512KB Abort
Level 2 RAM ECC 0x0840_0000 0x087F_FFFF 4MB 512KB
Accelerator Coherency Port
Accelerator Coherency Port 0x0800_0000 0x087F_FFFF 8MB 512KB Abort
Level 1 Cache Memories
Cortex-R5F Data Cache Memory 0x3000_0000 0x30FF_FFFF 16MB 32KB  Abort
Cortex-R5F Instruction Cache Memory 0x3100_0000 0x31FF_FFFF 16MB 32KB
External Memory Accesses
EMIF Chip Select 2 (asynchronous) 0x6000_0000 0x63FF_FFFF 64MB 16MB Access to "Reserved" space will generate Abort
EMIF Chip Select 3 (asynchronous) 0x6400_0000 0x67FF_FFFF 64MB 16MB
EMIF Chip Select 4 (asynchronous) 0x6800_0000 0x6BFF_FFFF 64MB 16MB
EMIF Chip Select 0 (synchronous) 0x8000_0000 0x87FF_FFFF 128MB 128MB
Flash OTP, ECC, EEPROM Bank
Customer OTP, Bank0 0xF000_0000 0xF000_1FFF 8KB 4KB Abort
Customer OTP, Bank1 0xF000_2000 0xF000_3FFF 8KB 4KB
Customer OTP, EEPROM Bank 0xF000_E000 0xF000_FFFF 8KB 1KB
Customer OTP-ECC, Bank0 0xF004_0000 0xF004_03FF 1KB 512B
Customer OTP-ECC, Bank1 0xF004_0400 0xF004_07FF 1KB 512B
Customer OTP-ECC, EEPROM Bank 0xF004_1C00 0xF004_1FFF 1KB 128B
TI OTP, Bank0 0xF008_0000 0xF008_1FFF 8KB 4KB
TI OTP, Bank1 0xF008_2000 0xF008_3FFF 8KB 4KB
TI OTP, EEPROM Bank 0xF008_E000 0xF008_FFFF 8KB 1KB
TI OTP-ECC, Bank0 0xF00C_0000 0xF00C_03FF 1KB 512B
TI OTP-ECC, Bank1 0xF00C_0400 0xF00C_07FF 1KB 512B Abort
TI OTP-ECC, EEPROM Bank 0xF00C_1C00 0xF00C_1FFF 1KB 128B
EEPROM Bank-ECC 0xF010_0000 0xF01F_FFFF 1MB 16KB
EEPROM Bank 0xF020_0000 0xF03F_FFFF 2MB 128KB
Flash Data Space ECC 0xF040_0000 0xF05F_FFFF 2MB 512KB
Interconnect SDC MMR
Interconnect SDC MMR 0xFA00_0000 0xFAFF_FFFF 16MB 16MB
Registers/Memories under PCR2 (Peripheral Segment 2)
CPPI Memory Slave (Ethernet RAM) PCS[41] 0xFC52_0000 0xFC52_1FFF 8KB 8KB Abort
CPGMAC Slave (Ethernet Slave) PS[30]-PS[31] 0xFCF7_8000 0xFCF7_87FF 2KB 2KB No Error
CPGMACSS Wrapper (Ethernet Wrapper) PS[29] 0xFCF7_8800 0xFCF7_88FF 256B 256B No Error
Ethernet MDIO Interface PS[29] 0xFCF7_8900 0xFCF7_89FF 256B 256B No Error
ePWM1 PS[28] 0xFCF7_8C00 0xFCF7_8CFF 256B 256B Abort
ePWM2 0xFCF7_8D00 0xFCF7_8DFF 256B 256B Abort
ePWM3 0xFCF7_8E00 0xFCF7_8EFF 256B 256B Abort
ePWM4 0xFCF7_8F00 0xFCF7_8FFF 256B 256B Abort
ePWM5 PS[27] 0xFCF7_9000 0xFCF7_90FF 256B 256B Abort
ePWM6 0xFCF7_9100 0xFCF7_91FF 256B 256B Abort
ePWM7 0xFCF7_9200 0xFCF7_92FF 256B 256B Abort
eCAP1 0xFCF7_9300 0xFCF7_93FF 256B 256B Abort
eCAP2 PS[26] 0xFCF7_9400 0xFCF7_94FF 256B 256B Abort
eCAP3 0xFCF7_9500 0xFCF7_95FF 256B 256B Abort
eCAP4 0xFCF7_9600 0xFCF7_96FF 256B 256B Abort
eCAP5 0xFCF7_9700 0xFCF7_97FF 256B 256B Abort
eCAP6 PS[25] 0xFCF7_9800 0xFCF7_98FF 256B 256B Abort
eQEP1 0xFCF7_9900 0xFCF7_99FF 256B 256B Abort
eQEP2 0xFCF7_9A00 0xFCF7_9AFF 256B 256B Abort
PCR2 registers PPSE[4]–PPSE[5] 0xFCFF_1000 0xFCFF_17FF 2KB 2KB Reads return zeros, writes have no effect
NMPU (EMAC) PPSE[6] 0xFCFF_1800 0xFCFF_18FF 512B 512B Abort
EMIF Registers PPS[2] 0xFCFF_E800 0xFCFF_E8FF 256B 256B Abort
Cyclic Redundancy Checker (CRC) Module Register Frame
CRC1 0xFE00_0000 0xFEFF_FFFF 16MB 512KB Accesses above 0xFE000200 generate abort.
CRC2 0xFB00_0000 0xFBFF_FFFF 16MB 512KB Accesses above 0xFB000200 generate abort.
Memories under User PCR3 (Peripheral Segment 3)
MIBSPI5 RAM PCS[5] 0xFF0A_0000 0xFF0B_FFFF 128KB 2KB Abort for accesses above 2KB
MIBSPI4 RAM PCS[3] 0xFF06_0000 0xFF07_FFFF 128KB 2KB Abort for accesses above 2KB
MIBSPI3 RAM PCS[6] 0xFF0C_0000 0xFF0D_FFFF 128KB 2KB Abort for accesses above 2KB
MIBSPI2 RAM PCS[4] 0xFF08_0000 0xFF09_FFFF 128KB 2KB Abort for accesses above 2KB
MIBSPI1 RAM PCS[7] 0xFF0E_0000 0xFF0F_FFFF 128KB 4KB Abort for accesses above 4KB
DCAN4 RAM PCS[12] 0xFF18_0000 0xFF19_FFFF 128KB 8KB Abort generated for accesses beyond offset 0x2000
DCAN3 RAM PCS[13] 0xFF1A_0000 0xFF1B_FFFF 128KB 8KB Abort generated for accesses beyond offset 0x2000
DCAN2 RAM PCS[14] 0xFF1C_0000 0xFF1D_FFFF 128KB 8KB Abort generated for accesses beyond offset 0x2000
DCAN1 RAM PCS[15] 0xFF1E_0000 0xFF1F_FFFF 128KB 8KB Abort generated for accesses beyond offset 0x2000.
MIBADC2 RAM PCS[29] 0xFF3A_0000 0xFF3B_FFFF 128KB 8KB Wrap around for accesses to unimplemented address offsets lower than 0x1FFF.
MIBADC1 RAM PCS[31] 0xFF3E_0000 0xFF3F_FFFF 128KB 8KB Wrap around for accesses to unimplemented address offsets lower than 0x1FFF.
MIBADC1 Look-UP Table 384 bytes Look-Up Table for ADC1 wrapper. Starts at address offset 0x2000 and ends at address offset 0x217F. Wrap around for accesses between offsets 0x0180 and 0x3FFF. Abort generation for accesses beyond offset 0x4000.
NHET2 RAM PCS[34] 0xFF44_0000 0xFF45_FFFF 128KB 16KB Wrap around for accesses to unimplemented address offsets lower than 0x3FFF. Abort generated for accesses beyond 0x3FFF.
NHET1 RAM PCS[35] 0xFF46_0000 0xFF47_FFFF 128KB 16KB Wrap around for accesses to unimplemented address offsets lower than 0x3FFF. Abort generated for accesses beyond 0x3FFF.
HET TU2 RAM PCS[38] 0xFF4C_0000 0xFF4D_FFFF 128KB 1KB Abort
HET TU1 RAM PCS[39] 0xFF4E_0000 0xFF4F_FFFF 128KB 1KB Abort
FlexRay TU RAM PCS[40] 0xFF50_0000 0xFF51_FFFF 128KB 1KB Abort
CoreSight Debug Components
CoreSight Debug ROM CSCS[0] 0xFFA0_0000 0xFFA0_0FFF 4KB 4KB Reads return zeros, writes have no effect
Cortex-R5F Debug CSCS[1] 0xFFA0_1000 0xFFA0_1FFF 4KB 4KB Reads return zeros, writes have no effect
ETM-R5 CSCS[2] 0xFFA0_2000 0xFFA0_2FFF 4KB 4KB Reads return zeros, writes have no effect
CoreSight TPIU CSCS[3] 0xFFA0_3000 0xFFA0_3FFF 4KB 4KB Reads return zeros, writes have no effect
POM CSCS[4] 0xFFA0_4000 0xFFA0_4FFF 4KB 4KB Reads return zeros, writes have no effect
CTI1 CSCS[7] 0xFFA0_7000 0xFFA0_7FFF 4KB 4KB Reads return zeros, writes have no effect
CTI3 CSCS[9] 0xFFA0_9000 0xFFA0_9FFF 4KB 4KB Reads return zeros, writes have no effect
CTI4 CSCS[10] 0xFFA0_A000 0xFFA0_AFFF 4KB 4KB Reads return zeros, writes have no effect
CSTF CSCS[11] 0xFFA0_B000 0xFFA0_BFFF 4KB 4KB Reads return zeros, writes have no effect
Registers under PCR3 (Peripheral Segment 3)
PCR3 registers PS[31:30] 0xFFF7_8000 0xFFF7_87FF 2KB 2KB Reads return zeros, writes have no effect
FTU PS[23] 0xFFF7_A000 0xFFF7_A1FF 512B 512B Reads return zeros, writes have no effect
HTU1 PS[22] 0xFFF7_A400 0xFFF7_A4FF 256B 256B Abort
HTU2 PS[22] 0xFFF7_A500 0xFFF7_A5FF 256B 256B Abort
NHET1 PS[17] 0xFFF7_B800 0xFFF7_B8FF 256B 256B Reads return zeros, writes have no effect
NHET2 PS[17] 0xFFF7_B900 0xFFF7_B9FF 256B 256B Reads return zeros, writes have no effect
GIO PS[16] 0xFFF7_BC00 0xFFF7_BCFF 256B 256B Reads return zeros, writes have no effect
MIBADC1 PS[15] 0xFFF7_C000 0xFFF7_C1FF 512B 512B Reads return zeros, writes have no effect
MIBADC2 PS[15] 0xFFF7_C200 0xFFF7_C3FF 512B 512B Reads return zeros, writes have no effect
FlexRay PS[12]+PS[13] 0xFFF7_C800 0xFFF7_CFFF 2KB 2KB Reads return zeros, writes have no effect
I2C1 PS[10] 0xFFF7_D400 0xFFF7_D4FF 256B 256B Reads return zeros, writes have no effect
I2C2 PS[10] 0xFFF7_D500 0xFFF7_D5FF 256B 256B Reads return zeros, writes have no effect
DCAN1 PS[8] 0xFFF7_DC00 0xFFF7_DDFF 512B 512B Reads return zeros, writes have no effect
DCAN2 PS[8] 0xFFF7_DE00 0xFFF7_DFFF 512B 512B Reads return zeros, writes have no effect
DCAN3 PS[7] 0xFFF7_E000 0xFFF7_E1FF 512B 512B Reads return zeros, writes have no effect
DCAN4 PS[7] 0xFFF7_E200 0xFFF7_E3FF 512B 512B Reads return zeros, writes have no effect
LIN1 PS[6] 0xFFF7_E400 0xFFF7_E4FF 256B 256B Reads return zeros, writes have no effect
SCI3 PS[6] 0xFFF7_E500 0xFFF7_E5FF 256B 256B Reads return zeros, writes have no effect
LIN2 PS[6] 0xFFF7_E600 0xFFF7_E6FF 256B 256B Reads return zeros, writes have no effect
SCI4 PS[6] 0xFFF7_E700 0xFFF7_E7FF 256B 256B Reads return zeros, writes have no effect
MibSPI1 PS[2] 0xFFF7_F400 0xFFF7_F5FF 512B 512B Reads return zeros, writes have no effect
MibSPI2 PS[2] 0xFFF7_F600 0xFFF7_F7FF 512B 512B Reads return zeros, writes have no effect
MibSPI3 PS[1] 0xFFF7_F800 0xFFF7_F9FF 512B 512B Reads return zeros, writes have no effect
MibSPI4 PS[1] 0xFFF7_FA00 0xFFF7_FBFF 512B 512B Reads return zeros, writes have no effect
MibSPI5 PS[0] 0xFFF7_FC00 0xFFF7_FDFF 512B 512B Reads return zeros, writes have no effect
System Modules Control Registers and Memories under PCR1 (Peripheral Segment 1)
DMA RAM PPCS[0] 0xFFF8_0000 0xFFF8_0FFF 4KB 4KB Abort
VIM RAM PPCS[2] 0xFFF8_2000 0xFFF8_2FFF 4KB 4KB Wrap around for accesses to unimplemented address offsets lower than 0x2FFF.
RTP RAM PPCS[3] 0xFFF8_3000 0xFFF8_3FFF 4KB 4KB Abort
Flash Wrapper PPCS[7] 0xFFF8_7000 0xFFF8_7FFF 4KB 4KB Abort
eFuse Farm Controller PPCS[12] 0xFFF8_C000 0xFFF8_CFFF 4KB 4KB Abort
Power Domain Control (PMM) PPSE[0] 0xFFFF_0000 0xFFFF_01FF 512B 512B Abort
FMTM
Note: This module is only used by TI during test		 PPSE[1] 0xFFFF_0400 0xFFFF_05FF 512B 512B Reads return zeros, writes have no effect
STC2 (NHET1/2) PPSE[2] 0xFFFF_0800 0xFFFF_08FF 256B 256B Reads return zeros, writes have no effect
SCM PPSE[2] 0xFFFF_0A00 0xFFFF_0AFF 256B 256B Abort
EPC PPSE[3] 0xFFFF_0C00 0xFFFF_0FFF 1KB 1KB Abort
PCR1 registers PPSE[4]–PPSE[5] 0xFFFF_1000 0xFFFF_17FF 2KB 2KB Reads return zeros, writes have no effect
NMPU (PS_SCR_S) PPSE[6] 0xFFFF_1800 0xFFFF_19FF 512B 512B Abort
NMPU (DMA Port A) PPSE[6] 0xFFFF_1A00 0xFFFF_1BFF 512B 512B Abort
Pin Mux Control (IOMM) PPSE[7] 0xFFFF_1C00 0xFFFF_1FFF 2KB 1KB Reads return zeros, writes have no effect
System Module - Frame 2 (see the TRMSPNU563) PPS[0] 0xFFFF_E100 0xFFFF_E1FF 256B 256B Reads return zeros, writes have no effect
PBIST PPS[1] 0xFFFF_E400 0xFFFF_E5FF 512B 512B Reads return zeros, writes have no effect
STC1 (Cortex-R5F) PPS[1] 0xFFFF_E600 0xFFFF_E6FF 256B 256B Reads return zeros, writes have no effect
DCC1 PPS[3] 0xFFFF_EC00 0xFFFF_ECFF 256B 256B Reads return zeros, writes have no effect
DMA PPS[4] 0xFFFF_F000 0xFFFF_F3FF 1KB 1KB Abort
DCC2 PPS[5] 0xFFFF_F400 0xFFFF_F4FF 256B 256B Reads return zeros, writes have no effect
ESM register PPS[5] 0xFFFF_F500 0xFFFF_F5FF 256B 256B Reads return zeros, writes have no effect
CCM-R5F PPS[5] 0xFFFF_F600 0xFFFF_F6FF 256B 256B Reads return zeros, writes have no effect
DMM PPS[5] 0xFFFF_F700 0xFFFF_F7FF 256B 256B Reads return zeros, writes have no effect
L2RAMW PPS[6] 0xFFFF_F900 0xFFFF_F9FF 256B 256B Abort
RTP PPS[6] 0xFFFF_FA00 0xFFFF_FAFF 256B 256B Reads return zeros, writes have no effect
RTI + DWWD PPS[7] 0xFFFF_FC00 0xFFFF_FCFF 256B 256B Reads return zeros, writes have no effect
VIM PPS[7] 0xFFFF_FD00 0xFFFF_FEFF 512B 512B Reads return zeros, writes have no effect
System Module - Frame 1 (see the TRMSPNU563) PPS[7] 0xFFFF_FF00 0xFFFF_FFFF 256B 256B Reads return zeros, writes have no effect