ZHCSFE6A
February 2013 – August 2016
TMS320DM369
PRODUCTION DATA.
1
TMS320DM369 数字媒体片上系统 (DMSoC)
1.1
特性
1.2
应用
1.3
说明
1.4
功能框图
2
修订历史记录
3
Device Overview
3.1
Device Comparison
3.2
Device Characteristics
3.3
Device Compatibility
3.4
ARM Subsystem Overview
3.4.1
Components of the ARM Subsystem
3.4.2
ARM926EJ-S RISC CPU
3.4.3
CP15
3.4.4
MMU
3.4.5
Caches and Write Buffer
3.4.6
Tightly Coupled Memory (TCM)
3.4.7
Advanced High-performance Bus (AHB)
3.4.8
Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
3.4.9
ARM Memory Mapping
3.4.9.1
ARM Internal Memories
3.4.9.2
External Memories
3.4.10
Peripherals
3.4.11
ARM Interrupt Controller (AINTC)
3.5
System Control Module
3.6
Power Management
3.7
Memory Map Summary
3.8
Pin Assignments
3.8.1
Pin Map (Bottom View)
3.9
Terminal Functions
4
Device Configurations
4.1
System Module Registers
4.2
Boot Modes
4.2.1
Boot Modes Overview
4.3
Device Clocking
4.3.1
Overview
4.3.2
PLL Controller Module
4.3.3
PLLC1
4.3.4
PLLC2
4.3.5
Processing, Video, EDMA and DDR EMIF Subsystems Maximum Operating Frequencies
4.3.6
PLL Controller Clocking Configurations Examples
4.3.7
Peripheral Clocking Considerations
4.4
Power and Sleep Controller (PSC)
4.5
Pin Multiplexing
4.6
Device Reset
4.7
Default Device Configurations
4.7.1
Device Configuration Pins
4.7.2
PLL Configuration
4.7.3
Power Domain and Module State Configuration
4.7.4
ARM Boot Mode Configuration
4.7.5
AEMIF Configuration
4.7.5.1
AEMIF Pin Configuration
4.7.5.2
AEMIF Timing Configuration
4.7.6
Oscillator Frequency Configuration
4.8
Debugging Considerations
4.8.1
Pullup/Pulldown Resistors
5
System Interconnect
6
Device Operating Conditions
6.1
Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted)
7
Peripheral Information and Electrical Specifications
7.1
Parameter Information Device-Specific Information
7.1.1
Signal Transition Levels
7.1.2
Timing Parameters and Board Routing Analysis
7.2
Recommended Clock and Control Signal Transition Behavior
7.3
Power Supplies
7.4
Power-Supply Sequencing
7.4.1
Simple Power-On and Power-Off Method
7.4.2
Restricted Power-On and Power-Off Method
7.4.3
Power-Supply Design Considerations
7.4.4
Power-Supply Decoupling
7.5
Reset
7.5.1
Reset Electrical Data/Timing
7.6
Oscillators and Clocks
7.6.1
MXI1 Oscillator
7.6.2
Clock PLL Electrical Data/Timing (Input and Output Clocks)
7.6.3
PRTCSS Oscillator
7.6.4
PRTCSS Electrical Data/Timing
7.7
Power Management and Real Time Clock Subsystem (PRTCSS)
7.7.1
PRTCSS Peripheral Register Description
7.8
General-Purpose Input/Output (GPIO)
7.8.1
GPIO Peripheral Register Description
7.8.2
GPIO Peripheral Input/Output Electrical Data/Timing
7.8.3
GPIO Peripheral External Interrupts Electrical Data/Timing
7.9
EDMA Controller
7.9.1
EDMA Channel Synchronization Events
7.9.2
EDMA Peripheral Register Description
7.10
External Memory Interface (EMIF)
7.10.1
Asynchronous EMIF (AEMIF)
7.10.1.1
NAND (NAND, SmartMedia, xD)
7.10.1.2
OneNAND
7.10.1.3
EMIF Peripheral Register Descriptions
7.10.1.4
AEMIF Electrical Data/Timing
7.10.2
DDR2/mDDR Memory Controller
7.10.3
DDR2/mDDR Memory Controller Electrical Data/Timing
7.10.3.1
DDR2/mDDR Routing Specifications
7.10.3.1.1
DDR2/mDDR Interface
7.10.3.1.2
DDR2/mDDR Interface Schematic
7.10.3.1.3
Compatible JEDEC DDR2/mDDR Devices
7.10.3.1.4
PCB Stack Up
7.10.3.1.5
Placement
7.10.3.1.6
DDR2/mDDR Keep Out Region
7.10.3.1.7
Bulk Bypass Capacitors
7.10.3.1.8
High-Speed Bypass Capacitors
7.10.3.1.9
Net Classes
7.10.3.1.10
DDR2/mDDR Signal Termination
7.10.3.1.11
VREF Routing
7.10.3.1.12
DDR2/mDDR CK and ADDR_CTRL Routing
7.11
MMC/SD
7.11.1
MMC/SD Peripheral Register Description
7.11.2
MMC/SD Electrical Data/Timing
7.12
Video Processing Subsystem (VPSS) Overview
7.12.1
Video Processing Front-End (VPFE)
7.12.1.1
Image Sensor Interface (ISIF)
7.12.1.2
The Image Pipe Interface (IPIPEIF)
7.12.1.3
Image Pipe - Hardware Image Signal Processor (IPIPE)
7.12.1.4
Hardware 3A (H3A)
7.12.1.5
Face Detection Module
7.12.1.6
VPFE Electrical Data/Timing
7.12.2
Video Processing Back-End (VPBE)
7.12.2.1
On-Screen Display (OSD)
7.12.2.2
Video Encoder / Digital LCD Controller (VENC/DLCD)
7.12.2.3
VPBE Electrical Data/Timing
7.12.2.4
High-Definition (HD) DACs and Video Buffer Electrical Data/Timing
7.12.2.4.1
HD DACs-Only Option
7.12.2.4.2
DAC With Video Buffer Option
7.13
USB2.0
7.13.1
USB Peripheral Register Description
7.13.2
USB2.0 Electrical Data/Timing
7.14
Universal Asynchronous Receiver/Transmitter (UART)
7.14.1
UART Peripheral Register Description
7.14.2
UART Electrical Data/Timing
7.15
Serial Port Interface (SPI)
7.15.1
SPI Peripheral Register Description
7.15.2
SPI Electrical Data/Timing
7.15.2.1
Master Mode — General
7.15.2.2
Slave Mode — General
7.15.2.3
Master Mode — Additional
7.15.2.4
Slave Mode — Additional
7.16
Inter-Integrated Circuit (I2C)
7.16.1
I2C Peripheral Register Description
7.16.2
I2C Electrical Data/Timing
7.16.2.1
Inter-Integrated Circuits (I2C) Timing
7.17
Multichannel Buffered Serial Port (McBSP)
7.17.1
McBSP Peripheral Register Description
7.17.2
McBSP Electrical Data/Timing
7.17.2.1
multichannel Buffered Serial Port (McBSP) Timing
7.18
Timer
7.18.1
Timer Peripheral Register Description
7.18.2
Timer Electrical Data/Timing
7.19
Pulse Width Modulator (PWM)
7.19.1
PWM Peripheral Register Description
7.19.2
PWM0/1/2/3 Electrical/Timing Data
7.20
Real Time Out (RTO)
7.20.1
Real Time Out (RTO) Peripheral Register Description
7.20.2
RTO Electrical/Timing Data
7.21
Ethernet Media Access Controller (EMAC)
7.21.1
EMAC Peripheral Register Description
7.21.2
Ethernet Media Access Controller (EMAC) Electrical Data/Timing
7.22
Management Data Input/Output (MDIO)
7.22.1
MDIO Peripheral Register Description
7.22.2
Management Data Input/Output (MDIO) Electrical Data/Timing
7.23
Host-Port Interface (HPI) Peripheral
7.23.1
HPI Device-Specific Information
7.23.2
HPI Bus Master
7.23.3
HPI Peripheral Register Description
7.23.4
HPI Electrical Data/Timing
7.24
Key Scan
7.24.1
Key Scan Peripheral Register Description
7.24.1.1
Key Scan Registers
7.24.2
Key Scan Electrical Data/Timing
7.25
Analog-to-Digital Converter (ADC)
7.25.1
Analog-to-Digital Converter (ADC) Peripheral Register Description
7.25.1.1
Analog-to-Digital Converter (ADC) Interface Registers
7.26
Voice Codec
7.26.1
Voice Codec Register Description
7.26.1.1
Voice Codec Registers
7.27
IEEE 1149.1 JTAG
7.27.1
JTAG Register Description
7.27.2
JTAG Test-Port Electrical Data/Timing
8
器件和文档支持
8.1
开发工具
8.2
器件命名规则
8.3
文档支持
8.4
Community Resources
8.5
商标
8.6
静电放电警告
8.7
Glossary
9
机械封装和可订购产品信息
9.1
封装信息
9.2
ZCE 的热性能数据
封装选项
请参考 PDF 数据表获取器件具体的封装图。
机械数据 (封装 | 引脚)
ZCE|338
散热焊盘机械数据 (封装 | 引脚)
订购信息
zhcsfe6a_oa
2
修订历史记录
日期
修订版本
注释
2016 年 8 月
A
本文档的初始版本 - 外部(公开)