SLVSK31 June   2026 TLV9023L

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1.     Pin Configurations:TLV9023L
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
    4. 6.4 Device Functional Modes
      1. 6.4.1 Outputs
        1. 6.4.1.1 Comparator Open-Drain Outputs
        2. 6.4.1.2 AND_OUT Output
      2. 6.4.2 Power-On Reset (POR)
        1. 6.4.2.1 Output POR Behavior
      3. 6.4.3 Output Latching
        1. 6.4.3.1 TLV9023L Latch Behavior
        2. 6.4.3.2 Clear (CLR) Input
      4. 6.4.4 Inputs
        1. 6.4.4.1 Rail to Rail Input
        2. 6.4.4.2 Fail-Safe Inputs
        3. 6.4.4.3 Input Protection
        4. 6.4.4.4 Internal Hysteresis
        5. 6.4.4.5 AND_IN Input
        6. 6.4.4.6 Unused Inputs
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Basic Comparator Definitions
        1. 7.1.1.1 Operation
        2. 7.1.1.2 Propagation Delay
        3. 7.1.1.3 Overdrive Voltage
    2. 7.2 Typical Application
      1. 7.2.1 Window Comparator
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

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6.4.3.1 TLV9023L Latch Behavior

The TLV9023L output latches low during the POR period. Following the POR period, the output is latched low and must be cleared with a high-to-low transition on the CLR pin. The following is a summary of the latch operation.

TLV9023L Latch Timing ExampleFigure 6-2 Latch Timing Example

The following is a summary of the latch operation.

  1. Output is low during the POR period following first power-on.
  2. Input transition is ignored during POR period.
  3. Following the POR period, the OUT stays latched low.
  4. IN- passes IN+, but transition is ignored during latch.
  5. CLR falling edge resets and arms latch awaiting next transition.
  6. IN- > IN+, so OUT goes low and latches.
  7. IN+ > IN-, but OUT remains latched low.
  8. CLR falling edge resets and arms latch for next transition.
  9. IN- crosses IN+, output goes low and latches again.
  10. Output remains latched low even when IN+ > IN-.