Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
Because the TLV803 has an open-drain output, multiple TLV803 outputs can be directly tied together to form a logical OR-ing function for the RESET line. Only one pull-up resistor is required for this configuration. Figure 11 shows two TLV803s connected together to provide monitoring of a 3.3-V power rail and a 5.0-V power rail. A reset is generated if either power rail falls below the threshold voltage of its corresponding TLV803.
The RESET output of the TLV803 can be pulled to a maximum voltage of 6 V and can be pulled higher in voltage than VDD. It is useful to provide level shifting of the output for cases where the monitored voltage is less than the useful logic levels of the load. Figure 12 shows the TLV803Z used to monitor a 2.5-V power rail, with a logic RESET input to a microprocessor that is connected to 5.0 V and has 5.0-V logic levels.
Figure 13 shows TLV803S being used to monitor the supply rail for a DSP, FPGA, or ASIC.
This design calls for a 3.3-V rail to be monitored. The design resets if the supply rail falls below 2.93 V. The output must satisfy 3.3-V CMOS logic.
Select the TLV803S to satisfy the voltage threshold requirement.
Place a pullup resistor on RESET to VDD in order to satisfy the output logic requirement.