ZHCS187C April   2011  – September 2015 TLV803 , TLV853


  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. Device Comparison
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Thermal Information
    4. 7.4 Recommended Operating Conditions
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VDD Transient Rejection
      2. 8.3.2 Reset During Power Up and Power Down
      3. 8.3.3 Bidirectional Reset Pins
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation (VDD > Power-Up Reset Voltage)
      2. 8.4.2 Power On Reset (VDD < Power-Up Reset Voltage)
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Monitoring Multiple Supplies
      2. 9.1.2 Output Level Shifting
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 开发支持
        1. 评估模块
        2. Spice 模型
    2. 12.2 文档支持
      1. 12.2.1 相关文档
    3. 12.3 相关链接
    4. 12.4 社区资源
    5. 12.5 商标
    6. 12.6 静电放电警告
    7. 12.7 Glossary
  13. 13机械、封装和可订购信息


机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)

Application and Implementation


Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

Application Information

Monitoring Multiple Supplies

Because the TLV803 has an open-drain output, multiple TLV803 outputs can be directly tied together to form a logical OR-ing function for the RESET line. Only one pull-up resistor is required for this configuration. Figure 11 shows two TLV803s connected together to provide monitoring of a 3.3-V power rail and a 5.0-V power rail. A reset is generated if either power rail falls below the threshold voltage of its corresponding TLV803.

TLV803 TLV853 TLV863 ai_multiple_bvs157.gif Figure 11. Multiple Voltage Rail Monitoring

Output Level Shifting

The RESET output of the TLV803 can be pulled to a maximum voltage of 6 V and can be pulled higher in voltage than VDD. It is useful to provide level shifting of the output for cases where the monitored voltage is less than the useful logic levels of the load. Figure 12 shows the TLV803Z used to monitor a 2.5-V power rail, with a logic RESET input to a microprocessor that is connected to 5.0 V and has 5.0-V logic levels.

TLV803 TLV853 TLV863 ai_level_shift_bvs157.gif Figure 12. Output Voltage Level Shifting

Typical Application

Figure 13 shows TLV803S being used to monitor the supply rail for a DSP, FPGA, or ASIC.

TLV803 TLV853 TLV863 typ_app_bvs157.gif Figure 13. Typical Application

Design Requirements

This design calls for a 3.3-V rail to be monitored. The design resets if the supply rail falls below 2.93 V. The output must satisfy 3.3-V CMOS logic.

Detailed Design Procedure

Select the TLV803S to satisfy the voltage threshold requirement.

Place a pullup resistor on RESET to VDD in order to satisfy the output logic requirement.

Application Curves

TLV803 TLV853 TLV863 tc_pulse-overdrive_bvs157.gif Figure 14. Minimum Pulse Duration At VDD vs Overdrive Threshold Voltage vs Temperature Voltage