具有折返电流限制的 TLV740P 300mA 低压降稳压器
- ZHCSLF3A June 2020 – December 2020 TLV740P
  
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具有折返电流限制的 TLV740P 300mA 低压降稳压器

本资源的原文使用英文撰写。为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

折返过流保护
封装：
- 1mm × 1mm 4 引脚 X2SON
- 5 引脚 SOT-23 封装
超低压降：300mA 时为 460mV
精度：1%
低 I_Q：50µA
输入电压范围：1.4V 至 5.5V
可提供固定输出电压：
1V 至 3.3V
高 PSRR：1kHz 时为 65dB
有源输出放电

2 应用

3 说明

TLV740P 低压降 (LDO) 线性稳压器是一款低静态电流 LDO，具有出色的线路和负载瞬态性能，专为对功耗敏感的应用设计。此器件可提供 1% 的典型精度。

TLV740P 还可在器件上电和使能期间提供浪涌电流控制。TLV740P 将输入电流限制为定义的电流限值，从而防止从输入电源流出的电流过大。此功能对于电池供电类器件尤为重要。

TLV740P 采用标准的 DQN 和 DBV 封装。TLV740P 还提供了有源下拉电路，用于对输出负载进行快速放电。

器件信息⁽¹⁾

器件名称	封装	封装尺寸
TLV740P	SOT-23 (5)	2.90mm × 1.60mm
TLV740P	X2SON (4)	1.00mm × 1.00mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。

典型应用电路

压降电压与输出电流间的关系 (3.3V V_OUT)

4 Revision History

Changes from Revision * (June 2020) to Revision A (December 2020)

将 DQN 封装状态从预发布更改为量产数据Go

5 Pin Configuration and Functions

Figure 5-1 DQN Package, 4-Pin X2SON,Top View

Figure 5-2 DBV Package,5-Pin SOT-23,Top View

Table 5-1 Pin Functions

PIN			I/O	DESCRIPTION
NAME	NO.
NAME	X2SON	SOT-23
EN	3	3	I	Enable pin. Driving this pin to logic high enables the device; driving this pin to logic low disables the device. Do not float this pin. If not used, connect EN to IN.
GND	2	2	—	Ground pin. This pin must be connected to ground on the board.
IN	4	1	I	Input pin. For best transient response and to minimize input impedance, use the recommended value or larger ceramic capacitor from IN to ground; see the Recommended Operating Conditions table. Place the input capacitor as close to the input of the device as possible.
NC	—	4	—	No connect pin. This pin is not internally connected. Connect to ground for best thermal performance or leave floating.
OUT	1	5	O	Regulated output pin. A 1-µF or greater effective capacitance is required from OUT to ground for stability. see the Recommended Operating Conditions table. For best transient response, use a 1-µF or larger ceramic capacitor from OUT to ground. Place the output capacitor as close to output of the device as possible.
Thermal pad		—	—	The thermal pad is electrically connected to the GND pin. Connect the thermal pad to a large-area GND plane for improved thermal performance.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Voltage	V_IN	–0.3	6.0	V
	V_EN	–0.3	VIN⁽²⁾
	V_OUT	–0.3	V_IN + 0.3 or 3.6⁽³⁾
Temperature	Operating junction, T_J	–55	125	°C
Temperature	Storage, T_stg	–55	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Maximum is V_IN or smaller.

(3) Maximum is V_IN + 0.3 V or 3.6 V, whichever is smaller.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
V_IN	Input voltage	1.4	5.5	V
V_OUT	Output voltage	0	V_IN + 0.3	V
V_EN	Enable voltage	0	V_IN⁽¹⁾	V
I_OUT	Output current	0	300	mA
C_IN	Input capacitor	1		μF
C_OUT	Output capacitor⁽²⁾	1	100	μF
f_EN	Enable toggle frequency		10	kHz
T_J	Junction temperature	–40	85	°C

(1) V_EN is V_IN or smaller.

(2) Effective output capacitance of 0.5 µF minimum required for stability.

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		TLV740P		UNIT
		DQN (X2SON)	DBV (SOT-23-5)
		4 PINS	5 PINS
R_θJA	Junction-to-ambient thermal resistance	224.3	216	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	161.5	123.2	°C/W
R_θJB	Junction-to-board thermal resistance	164.6	88.2	°C/W
ψ_JT	Junction-to-top characterization parameter	10.9	62.2	°C/W
ψ_JB	Junction-to-board characterization parameter	164.0	87.8	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	154.8	N/A	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

at operating temperature range (T_J = +25°C), V_IN = V_OUT(NOM) + 2.1 V, I_OUT = 1 mA, V_EN = V_IN, and C_IN = C_OUT = 1 μF, (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
	Output accuracy	1 V ≤ V_OUT ≤ 3.3 V		–1		1	%
	Maximum output current⁽¹⁾					300	mA
	Output voltage temperature coefficient	I_OUT = 0.1 mA, –40°C ≤ T_J ≤ +85°C			0.0017		%/℃
	Line regulation	V_OUT(NOM) + 0.5 V ≤ V_IN ≤ 5.5 V			1	5	mV
	Load regulation	1 mA ≤ I_OUT ≤ 300 mA			10	30	mV
V_DO	Dropout voltage	V_OUT = 0.95 x V_OUT(nom)	1 V ≤ V_OUT< 1.8 V, I_OUT = 300 mA		1200	1300	mV
		V_OUT = 0.95 x V_OUT(nom)	1.8 V ≤ V_OUT < 2.1 V, I_OUT = 300 mA		700	800
		V_OUT = 0.95 x V_OUT(nom)	2.1 V ≤ V_OUT ≤ 3.3 V, I_OUT = 300 mA		460	500
I_GND	Ground current	I_OUT = 0 mA			50	80	µA
I_SHDN	Shutdown current	V_EN ≤ 0.4 V, 3.1 V ≤ V_IN ≤ 5.5 V, –40°C ≤ T_J ≤ +85°C			0.1	1	µA
PSRR	Power-supply rejection ratio	V_IN = 5.4 V, V_OUT = 3.3 V, I_OUT = 150 mA	f = 100 Hz		67		dB
			f = 10 kHz		45
			f = 1 MHz		32
Vn	Output noise voltage	BW = 100 Hz to 100 kHz, V_OUT = 1.0 V, I_OUT = 1 mA			65		µV_RMS
t_STR	Startup time⁽²⁾	C_OUT = 1 µF, I_OUT = 300 mA			100		µs
V_HI	EN pin high voltage (enabled)	–40°C ≤ T_J ≤ +85°C		1.0		V_IN	V
V_LO	EN pin low voltage (disabled)	–40°C ≤ T_J ≤ +85°C		0		0.4	V
I_EN	Enable pin current	EN = 5.5 V, –40°C ≤ T_J ≤ +85°C			10		nA
R_PULLDOWN	Pulldown resistance	V_IN = 5.5 V, V_EN = 0 V			120		Ω
I_CL	Output current limit			360			mA
I_SC	Short circuit current limit	V_OUT = 0 V			40		mA
T_SD(shutdown)	Thermal shutdown temperature	Shutdown, temperature increasing			158		°C
T_SD(reset)	Thermal shutdown reset temperature	Reset, temperature decreasing			140		°C

(1) Maximum output current is affected by the PCB layout, metal trace width, number of layers, ambient temperatrue and other environmental factors. Thermal limitations of the system must be carefully considered.

(2) Startup time = time from EN assertion to 0.95 × V_OUT(NOM).

6.6 Typical Characteristics

over operating temperature range (T_J = –40°C to 85°C), V_IN = V_OUT(nom) + 2.1 V, I_OUT = 1 mA, V_EN = V_IN, and C_IN = C_OUT = 1 µF (unless otherwise noted); typical values are at T_J = 25°C

Figure 6-1 Line Regulation vs V_IN

V_OUT = 1.0 V

Figure 6-3 Dropout Voltage vs I_OUT

V_OUT = 1.0 V

Figure 6-5 Dropout Voltage vs V_IN

V_OUT = 1.0 V

Figure 6-7 Foldback Current Limit vs I_OUT

V_OUT = 3.3 V

Figure 6-9 Foldback Current Limit vs I_OUT

V_OUT = 3.3 V

Figure 6-11 I_GND vs I_OUT

Figure 6-13 UVLO Rising and Falling Threshold vs Temperature

C_IN = open, V_OUT = 1.8 V

Figure 6-15 PSRR vs Frequency and I_OUT

Figure 6-17 Output Noise vs Frequency and V_OUT

V_IN = 3.9 V to 4.9 V, slew rate = 1 V/µs, V_EN = 1 V,
I_OUT = 150 mA

Figure 6-19 Line Transient

V_IN = 3.9 V, V_EN = 1 V, I_OUT = 1 mA to 150 mA,
slew rate = 1 A/µs

Figure 6-21 Load Transient

V_IN = 3.9 V, V_EN = 1 V, I_OUT = 1 mA to 300 mA,
slew rate = 1 A/µs

Figure 6-23 Load Transient

V_IN = 5.5 V, C_IN = open, I_OUT = open

Figure 6-25 Start-Up With EN, Inrush Current

V_IN = 5.5 V, V_EN = 1 V to 0 V, I_OUT = open

Figure 6-27 Shutdown Response With Enable

Figure 6-2 Load Regulation vs I_OUT

V_OUT = 3.3 V

Figure 6-4 Dropout Voltage vs I_OUT

V_OUT = 3.3 V

Figure 6-6 Dropout Voltage vs V_IN

V_OUT = 1.8 V

Figure 6-8 Foldback Current Limit vs I_OUT

V_OUT = 3.3 V, I_OUT = 0 mA

Figure 6-10 I_GND vs V_IN

V_IN = 5.5 V

Figure 6-12 EN High and Low Threshold vs Temperature

C_IN = open, V_OUT = 1.0 V

Figure 6-14 PSRR vs Frequency and I_OUT

C_IN = open, V_OUT = 3.3 V

Figure 6-16 PSRR vs Frequency and I_OUT

V_IN = 3.9 V to 4.9 V, slew rate = 1 V/µs, V_EN = 1 V, I_OUT = 1 mA

Figure 6-18 Line Transient

V_IN = 3.9 V to 4.9 V, slew rate = 1 V/µs, V_EN = 1 V,
I_OUT = 300 mA

Figure 6-20 Line Transient

V_IN = 3.9 V, V_EN = 1 V, I_OUT = 1 mA to 150 mA,
slew rate = 1 A/µs, rising edge

Figure 6-22 Load Transient

V_IN = 3.9 V, V_EN = 1 V, I_OUT = 1 mA to 300 mA,
slew rate = 1 A/µs, rising edge

Figure 6-24 Load Transient

V_IN = 0 V to 5.5 V to 0 V, I_OUT = 150 mA

Figure 6-26 Start-Up and Shutdown

7 Detailed Description

7.1 Overview

The TLV740P is a cost-effective low-dropout (LDO) regulator that consumes low quiescent current and delivers excellent line and load transient performance. These characteristics make the device ideal for a wide range of portable applications.

This LDO offers foldback current limit, output enable, active discharge, undervoltage lockout (UVLO), and thermal protection.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Foldback Current Limit

The device has an internal current limit circuit that protects the regulator during transient high-load current faults or shorting events. The current limit is a hybrid brickwall-foldback scheme. The current limit transitions from a brickwall scheme to a foldback scheme at the foldback voltage (V_FOLDBACK). In a high-load current fault with the output voltage above V_FOLDBACK, the brickwall scheme limits the output current to the current limit (I_CL). When the voltage drops below V_FOLDBACK, a foldback current limit activates that scales back the current as the output voltage approaches GND. When the output is shorted, the device supplies a typical current called the short-circuit current limit (I_SC). I_CL and I_SC are listed in the Electrical Characteristics table.

For this device, V_FOLDBACK = 0.95 V × V_OUT(NOM).

The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the device begins to heat up because of the increase in power dissipation. When the device is in brickwall current limit, the pass transistor dissipates power [(V_IN – V_OUT) × I_CL]. When the device output is shorted and the output is below V_FOLDBACK, the pass transistor dissipates power [(V_IN – V_OUT) × I_SC]. If thermal shutdown is triggered, the device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If the output current fault condition continues, the device cycles between current limit and thermal shutdown. For more information on current limits, see the Know Your Limits application report.

Figure 7-1 shows a diagram of the foldback current limit.

Figure 7-1 Foldback Current Limit

7.3.2 Output Enable

The enable pin (EN) is active high. Enable the device by forcing the voltage of the enable pin to exceed the minimum EN pin high-level input voltage (see the Electrical Characteristics table). Turn off the device by forcing the voltage of the enable pin to drop below the maximum EN pin low-level input voltage (see the Electrical Characteristics table). If shutdown capability is not required, connect EN to IN.

This device has an internal pulldown circuit that activates when the device is disabled to actively discharge the output voltage.