ZHCSHH2B January   2018  – October 2018 TLV6710

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
    1.     Device Images
      1.      简化框图
  4. 修订历史记录
  5. 器件比较表
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Inputs (INA, INB)
      2. 8.3.2 Outputs (OUTA, OUTB)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation (VDD > UVLO)
      2. 8.4.2 Undervoltage Lockout (V(POR) < VDD < UVLO)
      3. 8.4.3 Power On Reset (VDD < V(POR))
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Window Comparator Considerations
      2. 9.1.2 Input and Output Configurations
      3. 9.1.3 Immunity to Input Pin Voltage Transients
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 Do's and Don'ts
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 开发支持
    2. 12.2 文档支持
      1. 12.2.1 相关文档
    3. 12.3 接收文档更新通知
    4. 12.4 社区资源
    5. 12.5 商标
    6. 12.6 静电放电警告
    7. 12.7 术语表
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Detailed Design Procedure

  1. Determine the minimum total resistance of the resistor network necessary to achieve the current consumption specification by using Equation 1. For this example, the current flow through the resistor network was chosen to be 13 µA; a lower current can be selected, however, care should be taken to avoid leakage currents that are artifacts of the manufacturing process. Leakage currents significantly impact the accuracy if they are greater than 1% of the resistor network current.
  2. Equation 5. TLV6710 RTotal_eqn.gif

    where

    • VMON(OV) is the target voltage at which an overvoltage condition is detected as VMON rises.
    • I is the current flowing through the resistor network.
  3. After RTOTAL is determined, R3 can be calculated using Equation 6. Select the nearest 1% resistor value for R3. In this case, 30.9 kΩ is the closest value.
  4. Equation 6. TLV6710 R3_eqn.gif
  5. Use Equation 7 to calculate R2. Select the nearest 1% resistor value for R2. In this case, 6.81 kΩ is the closest value.
  6. Equation 7. TLV6710 R2_eqn.gif
  7. Use Equation 8 to calculate R1. Select the nearest 1% resistor value for R1. In this case, 2 MΩ is the closest value.
  8. Equation 8. TLV6710 R1_eqn.gif
  9. The worst-case tolerance can be calculated by referring to Equation 13 in application report Optimizing Resistor Dividers at a Comparator Input (SLVA450). An example of the rising threshold error, VMON(OV), is given in Equation 9:
  10. Equation 9. TLV6710 tolerance_eqn.gif

    where

    • % TOL(VIT+(INB)) is the tolerance of the INB positive threshold.
    • % ACC is the total tolerance of the VMON(OV) voltage.
    • % TOLR is the tolerance of the resistors selected.
  11. When the outputs switch to the high-Z state, the rise time of the OUTA or OUTB node depends on the pullup resistance and the capacitance on the node. Choose pullup resistors that satisfy the downstream timing requirements; 100-kΩ resistors are a good choice for low-capacitive loads.