ZHCSHH2B January   2018  – October 2018 TLV6710

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化框图
  4. 4 修订历史记录
  5. 5 器件比较表
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Inputs (INA, INB)
      2. 8.3.2 Outputs (OUTA, OUTB)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation (VDD > UVLO)
      2. 8.4.2 Undervoltage Lockout (V(POR) < VDD < UVLO)
      3. 8.4.3 Power On Reset (VDD < V(POR))
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Window Comparator Considerations
      2. 9.1.2 Input and Output Configurations
      3. 9.1.3 Immunity to Input Pin Voltage Transients
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 Do's and Don'ts
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 开发支持
    2. 12.2 文档支持
      1. 12.2.1 相关文档
    3. 12.3 接收文档更新通知
    4. 12.4 社区资源
    5. 12.5 商标
    6. 12.6 静电放电警告
    7. 12.7 术语表
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

9.1.1 Window Comparator Considerations

The inverting and noninverting configuration of the comparators forms a window-comparator detection circuit using a resistor divider network, as shown in Figure 19 and Figure 20. The input pins can monitor any system voltage above 400 mV with the use of a resistor divider network. INA and INB monitor for undervoltage and overvoltage conditions, respectively.

TLV6710 typ_app2_snvsav4.gifFigure 19. Window Comparator Block Diagram
TLV6710 ai_tim_window_comp_snvsav4.gifFigure 20. Window Comparator Timing Diagram

The TLV6710 flags the overvoltage or undervoltage condition with the greatest accuracy. The highest accuracy threshold voltages are VIT–(INA) and VIT+(INB), and correspond with the falling undervoltage flag, and the rising overvoltage flag, respectively. These thresholds represent the accuracy when the monitored voltage is within the valid window (both OUTA and OUTB are in a high-impedance state), and correspond to the VMON(UV) and VMON(OV) trigger voltages, respectively. If the monitored voltage is outside of the valid window (VMON is less than the undervoltage limit, VMON(UV), or greater than overvoltage limit, VMON(OV)), then the input threshold voltages to re-enter the valid window are VIT+(INA) or VIT–(INB), and correspond with the VMON(UV_HYS) and VMON(OV_HYS) monitored voltages, respectively.

The resistor divider values and target threshold voltage can be calculated by using Equation 1 through Equation 4:

Equation 1. RTOTAL = R1 + R2 + R3

Choose an RTOTAL value so that the current through the divider is approximately 100 times higher than the input current at the INA and INB pins. Resistors with high values minimize current consumption; however, the input bias current degrades accuracy if the current through the resistors is too low. See application report Optimizing Resistor Dividers at a Comparator Input (SLVA450), for details on sizing input resistors.

R3 is determined by Equation 2:

Equation 2. TLV6710 q_r3_snvsav4.gif

where

  • VMON(OV) is the target voltage at which an overvoltage condition is detected.

R2 is determined by either Equation 3 or Equation 4:

Equation 3. TLV6710 q_r2a_snvsav4.gif

where

  • VMON(UV_HYS) is the target voltage at which an undervoltage condition is removed as VMON rises.
Equation 4. TLV6710 q_r2b_snvsav4.gif

where

  • VMON(UV) is the target voltage at which an undervoltage condition is detected.