ZHCSFQ3B November   2016  – November 2017 TLV62568

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Save Mode
      2. 7.3.2 100% Duty Cycle Low Dropout Operation
      3. 7.3.3 Soft Startup
      4. 7.3.4 Switch Current Limit
      5. 7.3.5 Under Voltage Lockout
      6. 7.3.6 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Enabling/Disabling the Device
      2. 7.4.2 Power Good
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Setting the Output Voltage
        3. 8.2.2.3 Output Filter Design
        4. 8.2.2.4 Inductor Selection
        5. 8.2.2.5 Input and Output Capacitor Selection
      3. 8.2.3 Application Performance Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 使用 WEBENCH® 工具定制设计方案
    2. 11.2 文档支持
      1. 11.2.1 相关文档
    3. 11.3 接收文档更新通知
    4. 11.4 社区资源
    5. 11.5 商标
    6. 11.6 静电放电警告
    7. 11.7 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Layout

Layout Guidelines

The PCB layout is an important step to maintain the high performance of the TLV62568 device.

  • The input/output capacitors and the inductor should be placed as close as possible to the IC. This keeps the power traces short. Routing these power traces direct and wide results in low trace resistance and low parasitic inductance.
  • The low side of the input and output capacitors must be connected properly to the power GND to avoid a GND potential shift.
  • The sense traces connected to FB are signal traces. Special care should be taken to avoid noise being induced. Keep these traces away from SW nodes.
  • GND layers might be used for shielding.

Layout Example

TLV62568 TLV62568P TLV62568-9_Layout_DBV.gif Figure 20. TLV62568DBV Layout
TLV62568 TLV62568P TLV62568PDRL_Layout-4-DS-DBV_reference.gif Figure 21. TLV62568PDRL Layout

Thermal Considerations

Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, convection surfaces, and the presence of other heat-generating components affect the power dissipation limits of a given component.

Two basic approaches for enhancing thermal performance are listed below:

  • Improving the power dissipation capability of the PCB design
  • Introducing airflow in the system

For more details on how to use the thermal parameters, see the application notes: Thermal Characteristics Application Notes SZZA017 and SPRA953.