SLVSFL9 March   2020 TLV4011

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application Schematic
      2.      Block Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Dissipation Ratings
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 SENSE Monitoring
      2. 7.3.2 Transient Immunity
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Under-Voltage Detection
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Additional Application Information
        1. 8.2.2.1 Pull-up Resistor Selection
        2. 8.2.2.2 Input Supply Capacitor
        3. 8.2.2.3 Sense Capacitor
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOL Low-level output voltage VDD = 1.5 V, IOL = 1 mA 0.3 V
VDD = 3.3 V, IOL = 2 mA
VDD = 6 V, IOL = 3 mA
VPOR Power-up reset voltage(1) VOL(max) = 0.2 V, IOL = 50 μA, TA = 25°C 0.8 V
VIT Negative-going input threshold voltage(2) SENSE 1.2 1.226 1.244 V
Vhys Hysteresis TA = 25°C 15 mV
II Input current SENSE –25 25 nA
IOH High-level output current at RESET RESET SENSE = VIT + 0.2 V, VOH = VDD 300 nA
IDD Supply current VDD = 3.3 V, Output unconnected 2 4 μA
VDD = 6 V, Output unconnected 2 4
CI Input capacitance VI = 0 V to VDD 1 pF
(1) The lowest supply voltage at which RESET (VOL(max) = 0.2 V, IOL = 50 μA) becomes active. tr(VDD) ≥ 15 μs/V.
(2) To ensure the best stability of the threshold voltage, place a bypass capacitor (ceramic, 0.1-μF) near the supply terminals.