ZHCSLH6D June   2021  – July 2022 TLV3601-Q1 , TLV3602-Q1 , TLV3603-Q1

PRODMIX  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Diagrams
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Inputs
      2. 7.4.2 Push-Pull (Single-Ended) Output
      3. 7.4.3 Known Startup Condition
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Adjustable Hysteresis
      2. 8.1.2 Capacitive Loads
      3. 8.1.3 Latch Functionality
    2. 8.2 Typical Application
      1. 8.2.1 Implementing Hysteresis
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Optical Receiver
      3. 8.2.3 Over-Current Latch Condition
      4. 8.2.4 External Trigger Function for Oscilloscopes
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 接收文档更新通知
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 术语表
  12. 12Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Layout Guidelines

Comparators are very sensitive to input noise. For best results, adhere to the following layout guidelines.

  1. Use a printed-circuit-board (PCB) with a good, unbroken, low-inductance ground plane. Proper grounding (use of a ground plane) helps maintain specified device performance.

    Likewise, high performance board materials such as Rogers or high speed FR4 is also recommended.

  2. Place a decoupling capacitor (100-pF ceramic, surface-mount capacitor) between VCC and

    VEE as close to the device as possible. Using multiple bypass capacitors in different decade ranges such as 100-pF, 100-nF, and 1-µF provides the best noise reduction across frequency ranges.

  3. On the inputs and the output, keep lead lengths as short and minimize capacitive coupling to the traces by having a keepout area around the traces that is 3x the width of the traces. It is also recommended to keep inputs away from the output.
  4. Solder the device directly to the PCB rather than using a socket.