ZHCS851A March   2012  – September 2015 TLV320AIC3212

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用范围
  3. 3 描述
  4. 4 修订历史记录
  5. 5 说明 （续）
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics, SAR ADC
    6. 8.6  Electrical Characteristics, ADC
    7. 8.7  Electrical Characteristics, Bypass Outputs
    8. 8.8  Electrical Characteristics, Microphone Interface
    9. 8.9  Electrical Characteristics, Audio DAC Outputs
    10. 8.10 Electrical Characteristics, Class-D Outputs
    11. 8.11 Electrical Characteristics, Miscellaneous
    12. 8.12 Electrical Characteristics, Logic Levels
    13. 8.13 Audio Data Serial Interface Timing (I2S): I2S/LJF/RJF Timing in Master Mode
    14. 8.14 Audio Data Serial Interface Timing (I2S): I2S/LJF/RJF Timing in Slave Mode
    15. 8.15 Typical DSP Timing: DSP/Mono PCM Timing in Master Mode
    16. 8.16 Typical DSP Timing: DSP/Mono PCM Timing in Slave Mode
    17. 8.17 I2C Interface Timing
    18. 8.18 SPI Timing
    19. 8.19 Typical Characteristics
      1. 8.19.1 Audio ADC Performance
      2. 8.19.2 Audio DAC Performance
      3. 8.19.3 Class-D Driver Performance
      4. 8.19.4 MICBIAS Performance
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Device Connections
        1. 10.3.1.1 Digital Pins
        2. 10.3.1.2 Analog Pins
        3. 10.3.1.3 Multifunction Pins
      2. 10.3.2 Analog Audio I/O
        1. 10.3.2.1 Analog Low Power Bypass
        2. 10.3.2.2 Headphone Outputs
          1. 10.3.2.2.1 Using the Headphone Amplifier
          2. 10.3.2.2.2 Ground-Centered Headphone Amplifier Configuration
            1. 10.3.2.2.2.1 Circuit Topology
            2. 10.3.2.2.2.2 Charge Pump Setup and Operation
            3. 10.3.2.2.2.3 Output Power Optimization
            4. 10.3.2.2.2.4 Offset Correction and Start-Up
            5. 10.3.2.2.2.5 Ground-Centered Headphone Setup
              1. 10.3.2.2.2.5.1 High Audio Output Power, High Performance Setup
              2. 10.3.2.2.2.5.2 High Audio Output Power, Low Power Consumption Setup
              3. 10.3.2.2.2.5.3 Medium Audio Output Power, High Performance Setup
              4. 10.3.2.2.2.5.4 Lowest Power Consumption, Medium Audio Output Power Setup
          3. 10.3.2.2.3 Stereo Unipolar Configuration
            1. 10.3.2.2.3.1 Circuit Topology
            2. 10.3.2.2.3.2 Unipolar Turn-On Transient (Pop) Reduction
          4. 10.3.2.2.4 Mono Differential DAC to Mono Differential Headphone Output
        3. 10.3.2.3 Stereo Line Outputs
          1. 10.3.2.3.1 Line Out Amplifier Configurations
        4. 10.3.2.4 Differential Receiver Output
        5. 10.3.2.5 Stereo Class-D Speaker Outputs
      3. 10.3.3 ADC / Digital Microphone Interface
        1. 10.3.3.1 ADC Processing Blocks — Overview
          1. 10.3.3.1.1 ADC Processing Blocks
      4. 10.3.4 DAC
        1. 10.3.4.1 DAC Processing Blocks — Overview
          1. 10.3.4.1.1 DAC Processing Blocks
      5. 10.3.5 Device Power Consumption
      6. 10.3.6 Powertune
      7. 10.3.7 Clock Generation and PLL
      8. 10.3.8 Interfaces
        1. 10.3.8.1 Control Interfaces
          1. 10.3.8.1.1 I2C Control
          2. 10.3.8.1.2 SPI Control
        2. 10.3.8.2 Digital Audio Interfaces
      9. 10.3.9 Device Special Functions
    4. 10.4 Device Functional Modes
      1. 10.4.1 Recording Mode
      2. 10.4.2 Playback Mode
      3. 10.4.3 Analog Low Power Bypass Modes
    5. 10.5 Register Maps
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1 Charge Pump Flying and Holding Capacitor
        2. 11.2.2.2 Reference Filtering Capacitor
        3. 11.2.2.3 MICBIAS
      3. 11.2.3 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Examples
  14. 14器件和文档支持
    1. 14.1 文档支持
      1. 14.1.1 相关文档　
    2. 14.2 社区资源
    3. 14.3 商标
    4. 14.4 静电放电警告
    5. 14.5 Glossary
  15. 15机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

1 特性

  • 信噪比 (SNR) 为 101dB 的立体声音频数模转换器 (DAC)
  • 2.7mW 立体声 48kHz DAC 播放
  • SNR 为 93dB 的立体声音频 ADC
  • 5.6mW 立体声 48kHz ADC 录制
  • 8kHz 至 192kHz 播放和录制
  • 30mW DirectPath™耳机驱动器免除了对较大输出隔直电容的需要
  • 128mW 差分接收器输出驱动器
  • 立体声 D 类扬声器驱动器
    • 1.7W（8Ω，5.5V，10% THDN)
    • 1.4W（8Ω，5.5V，1% THDN）
  • 立体声线路输出
  • PowerTune™调整功率与 SNR 间的关系
  • 扩展信号处理选项
  • 8 个单端或 4 个全差分模拟输入
  • 立体声数字和模拟麦克风输入
  • 低功耗模拟旁路模式
  • 可编程锁相环 (PLL) 以及低频计时
  • 可编程 12 位逐次逼近 (SAR) ADC
  • SPI 和 I2C 控制接口
  • 三个独立数字音频串行接口
  • 4.81mm × 4.81mm × 0.625mm 81 焊球晶圆级芯片 (WCSP) (YZF) 封装

2 应用范围

  • 移动手持机
  • 平板电脑和电子书
  • 便携式导航设备 (PND)
  • 便携式媒体播放器 (PMP)
  • 便携式游戏系统
  • 便携式计算机

3 描述

TLV320AIC3212（也称 AIC3212）器件是一款灵活的高集成度、低功耗、低电压立体声音频编解码器。AIC3212 具有 数字麦克风输入和可编程输出、PowerTune 功能、可选音频处理模块、预定义和参数化的信号处理模块、集成 PLL 和灵活音频接口。凭借大量基于寄存器的控制（受控对象包括功率、输入和输出通道配置、增益、音效、引脚多路复用和时钟等），该器件能够精确满足其应用的要求。

器件信息(1)

器件型号 封装 封装尺寸（标称值）
TLV320AIC3212 DSBGA (81) 4.81mm x 4.81mm
  1. 要了解所有可用封装，请见数据表末尾的可订购产品附录。

简化框图

TLV320AIC3212 TLV320AIC3212_slas784.png