ZHCSRJ6C
June 2010 – January 2023
TLV320AIC3104-Q1
PRODUCTION DATA
1
特性
2
应用
3
说明
4
Revision History
5
说明(续)
6
Device Comparison
7
Pin Configuration and Functions
8
Specifications
8.1
Absolute Maximum Ratings
8.2
ESD Ratings
8.3
Recommended Operating Conditions
8.4
Thermal Information
8.5
Electrical Characteristics
8.6
Switching Characteristics I2S/LJF/RJF Timing in Master Mode
8.7
Switching Characteristics I2S/LJF/RJF Timing in Slave Mode
8.8
Switching Characteristics DSP Timing in Master Mode
8.9
Switching Characteristics DSP Timing in Slave Mode
8.10
Typical Characteristics
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagram
9.3
Feature Description
9.3.1
Audio Data Converters
9.3.2
Stereo Audio ADC
9.3.2.1
Stereo Audio ADC High-Pass Filter
9.3.3
Automatic Gain Control (AGC)
9.3.4
Stereo Audio DAC
9.3.5
Digital Audio Processing for Playback
9.3.6
Digital Interpolation Filter
9.3.7
Delta-Sigma Audio DAC
9.3.8
Audio DAC Digital Volume Control
9.3.9
Analog Output Common-mode Adjustment
9.3.10
Audio DAC Power Control
9.3.11
Audio Analog Inputs
9.3.12
Analog Input Bypass Path Functionality
9.3.13
ADC PGA Signal Bypass Path Functionality
9.3.14
Input Impedance and VCM Control
9.3.15
MICBIAS Generation
9.3.16
Analog Fully Differential Line Output Drivers
9.3.17
Analog High-Power Output Drivers
9.3.18
Short-Circuit Output Protection
9.3.19
Jack and Headset Detection
9.4
Device Functional Modes
9.4.1
Digital Audio Processing for Record Path
9.4.2
Increasing DAC Dynamic Range
9.4.3
Passive Analog Bypass During Power Down
9.4.4
Hardware Reset
9.5
Programming
9.5.1
Digital Control Serial Interface
9.5.2
I2C Control Interface
9.5.3
I2C Bus Debug in a Glitched System
9.5.4
Digital Audio Data Serial Interface
9.5.5
Right-Justified Mode
9.5.6
Left-Justified Mode
9.5.7
I2S Mode
9.5.8
DSP Mode
9.5.9
TDM Data Transfer
9.5.10
Audio Clock Generation
9.6
Register Maps
9.6.1
Output Stage Volume Controls
10
Application and Implementation
10.1
Application Information
10.2
Typical Applications
10.2.1
External Speaker Driver in Infotainment and Cluster Applications
10.2.1.1
Design Requirements
10.2.1.2
Detailed Design Procedure
10.2.1.3
Application Curves
10.2.2
External Speaker Amplifier With Separate Line Outputs
10.2.2.1
Design Requirements
10.2.2.2
Detailed Design Procedure
11
Power Supply Recommendations
12
Layout
12.1
Layout Guidelines
12.2
Layout Example
13
Device and Documentation Support
13.1
Device Support
13.1.1
Device Nomenclature
13.2
Documentation Support
13.2.1
Related Documentation
13.3
Receiving Notification of Documentation Updates
13.4
Community Resources
13.5
Trademarks
13.6
静电放电警告
14
Mechanical, Packaging, and Orderable Information
封装选项
机械数据 (封装 | 引脚)
RHB|32
MPQF130D
散热焊盘机械数据 (封装 | 引脚)
RHB|32
QFND029X
订购信息
zhcsrj6c_oa
zhcsrj6c_pm
1
特性
符合汽车应用要求
具有符合 AEC-Q100 标准的下列特性:
器件温度等级 3:–40°C 至 105°C
环境工作温度范围
器件 HBM ESD 分类等级 2
器件 CDM ESD 分类等级 C6
立体声音频 DAC:
102dBA 信噪比
16 位、20 位、24 位或 32 位数据
支持 8kHz 至 96kHz 的采样率
3D、低音、高音、EQ、去加重效果
提供灵活的节能模式和
性能
立体声音频 ADC:
92dBA 信噪比
支持 8kHz 至 96kHz 的采样率
在录音期间提供
数字信号处理和噪声滤除功能
六个音频输入引脚:
一对立体声单端输入
一对立体声全差分输入
六个音频输出驱动器:
全差动或单端立体声耳机驱动器
全差动立体声线路输出
低功耗:3.3V 模拟电源电压、14mW 立体声、48kHz 回放
具有无源模拟旁路的超低功耗模式
可编程输入/输出模拟增益
用于录音的自动增益控制 (AGC)
可编程麦克风偏置电平
用于灵活时钟生成的可编程锁相环路 (PLL)
I
2
C 控制总线
音频串行数据总线支持 I
2
S、左对齐/右对齐、DSP 和 TDM 模式
广泛的模块化电源控制
电源:
模拟:2.7V 至 3.6V
数字内核:1.525V 至 1.95V
数字 I/O:1.1V 至 3.6V