ZHCSHY2 March 2018 TLV320ADC3100
PRODUCTION DATA.
A typical EVM I2C register control script follows to show how to set up the TLV320ADC3100 in record mode with fS = 44.1 kHz and MCLK = 11.2896 MHz.
# Key: w 30 XX YY ==> write to I2C address 0x30, to register 0xXX, data 0xYY
# # ==> comment delimiter
#
# The following list gives an example sequence of items that must be executed in the time
# between powering the device up and reading data from the device. Note that there are
# other valid sequences depending on which features are used.
#
# ADC3101EVM Key Jumper Settings and Audio Connections:
# 1. Remove Jumpers W12 and W13
# 2. Insert Jumpers W4 and W5
# 3. Insert a 3.5mm stereo audio plug into J9 for
# single-ended input IN1L(P) - left channel and
# single-ended input IN1R(M) - right channel
################################################################
# 1. Define starting point:
# (a) Power up appicable external hardware power supplies
# (b) Set register page to 0
#
w 30 00 00
# (c) Initiate SW Reset
#
w 30 01 01
#
# 2. Program Clock Settings
# (a) Program PLL clock dividers P,J,D,R (if PLL is necessary)
#
# In EVM, the ADC3001 receives: MCLK = 11.2896 MHz,
# BCLK = 2.8224 MHz, WCLK = 44.1 kHz
#
# Sinve the sample rate is a multiple of the input MCLK then
# no PLL is needed thereby saving power. Use Default (Reset) Settings:
# ADC_CLKIN = MCLK, P=1, R=1, J=4, D=0000
w 30 04 00
w 30 05 11
w 30 06 04
w 30 07 00
w 30 08 00
#
# (b) Power up PLL (if PLL is necessary) - Not Used in this Example
w 30 05 11
# (c) Program and power up NADC
#
# NADC = 1, divider powered on
w 30 12 81
#
# (d) Program and power up MADC
#
# MADC = 2, divider powered on
w 30 13 82
#
# (e) Program OSR value
#
# AOSR = 128 (default)
w 30 14 80
#
# (f) Program I2S word length as required (16, 20, 24, 32 bits)
#
# mode is i2s, wordlength is 16, slave mode (default)
w 30 1B 00
#
# (g) Program the processing block to be used
#
# PRB_P1
w 30 3d 01
#
# 3. Program Analog Blocks
# (a) Set register Page to 1
#
w 30 00 01
#
# (b) Program MICBIAS if applicable
#
# Not used (default)
w 30 33 00
#
# (c) Program MICPGA
#
# Left Analog PGA Seeting = 0dB
w 30 3b 00
#
# Right Analog PGA Seeting = 0dB
w 30 3c 00
#
# (d) Routing of inputs/common mode to ADC input
# (e) Unmute analog PGAs and set analog gain
#
# Left ADC Input selection for Left PGA = IN1L(P) as Single-Ended
w 30 34 fc
#
# Right ADC Input selection for Right PGA = IN1R(M) as Single-Ended
w 30 37 fc
#
# 4. Program ADC
#
# (a) Set register Page to 0
#
w 30 00 00
#
# (b) Power up ADC channel
#
# Power-up Left ADC and Right ADC
w 30 51 c2
#
# (c) Unmute digital volume control and set gain = 0 dB
#
# UNMUTE
w 30 52 00
#