ZHCSEA1 October   2015 TLC59581

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用范围
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Pin Equivalent Input and Output Schematic Diagrams
      1. 7.1.1 Test Circuits
    2. 7.2 Timing Diagrams
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Device Functional Modes
      1. 8.3.1  Brightness Control (BC) Function
      2. 8.3.2  Color Brightness Control (CC) Function
      3. 8.3.3  Select RIREF For a Given BC
      4. 8.3.4  Choosing BC/CC For a Different Application
        1. 8.3.4.1 Example 1: Red LED Current is 20 mA, Green LED Needs 12 mA, Blue LED needs 8 mA
        2. 8.3.4.2 Example 2: Red LED Current is 5 mA, Green LED Needs 2 mA, Blue LED Needs 1 mA.
      5. 8.3.5  LED Open Detection (LOD)
      6. 8.3.6  Internal Circuit for Caterpillar Removal
      7. 8.3.7  Power Save Mode (PSM)
      8. 8.3.8  Internal Pre-Charge FET
      9. 8.3.9  Thermal Shutdown (TSD)
      10. 8.3.10 IREF Resistor Short Protection (ISP)
  9. 9 Application and Implementation
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 社区资源
    2. 12.2 相关链接
    3. 12.3 商标
    4. 12.4 静电放电警告
    5. 12.5 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

11 Layout

11.1 Layout Guidelines

  1. Place the decoupling capacitor near the VCC pin and GND plane.
  2. Place the current programming resistor RIREF close to IREF pin and IREFGND pin.
  3. Route the GND pattern as widely as possible for large GND currents. Maximum GND current is approximately 1.2 A.
  4. Routing between the LED cathode side and the device OUTXn pin should be as short and straight as possible to reduce wire inductance.
  5. The PowerPAD™ must be connected to GND plane because the pad is used as power ground pin internally, there will be large current flow through this pad when all channels turn on. Furthermore, this pad should be connected to a heat sink layer by thermal via to reduce device temperature. One suggested thermal via pattern is shown as below. For more information about suggested thermal via pattern and via size, see PowerPAD Thermally Enhanced Package, SLMA002G.
  6. MOSFETS must be placed in the in the middle of the board, which should be laid out as symmetrically as possible.

11.2 Layout Example

TLC59581 via_layout_SLVSCE7.gif