8.3.5.1 V_S Supply POR

The device is turned off and all register contents are lost if the V_S voltage drops below V_{POR_F}. To turn the device back on, the V_S voltage must be raised back above V_{POR_R}, as illustrated in Figure 12. The device then starts the initialization process as described in section Device Initialization .

Figure 12. V_S is Lowered Below The POR threshold, Then Ramped Back Up To Complete A POR Cycle

8.3.5.2 Hardware Reset

Microcontroller can toggle the RESET pin to perform a hardware reset to the device. The RESET pin is internally pulled-down via a 1MΩ resistor and must be kept low for normal operation. When the RESET pin is toggled high, the device enters the reset state with most of the internal blocks turned off and consumes very little current of I_{S_RESET}. Switch monitoring and SPI communications are stopped in the reset state, and all register contents are cleared. When RESET pin is toggled back low, all the registers are set to their default values and the device state machine is re-initialized, similar to a POR event. When the re-initialization process is completed, the INT pin is asserted low, and the interrupt register bit POR and the SPI status flag POR are both asserted to notify the microcontroller that the device has completed the reset process.

Note in order to successfully reset the device, the RESET pin needs to be kept high for a minimum duration of t_RESET. The pin is required to be driven with a stable input (below V_{RESET_L} for logic low or above V_{RESET_H} for logic H) to prevent the device from accidental reset.

8.3.5.3 Software Reset

In addition to hardware reset, the microcontroller can also issue a SPI command to initiate software reset. This is triggered by setting the RESET bit in the register CONFIG to logic 1, which re- initialized the device with all registers set to their default value. When the re-initialization process is completed, the INT pin is asserted low, and the interrupt register bit POR and the SPI status flag POR are both asserted to notify the microcontroller that the device has completed the reset process.

Table 1. TIC12400 Wetting Current and Threshold Setting Details

8.3.8.1 Input Current Source/Sink Selection

Among the 24 inputs, IN10 to IN23 are intended for monitoring only ground-connected switches and are connected to current sources. IN0 to IN9 can be programmed to monitor either ground-connected switches or supply-connected switches by configuring the CS_SELECT register. The default configuration of the IN0-IN9 inputs after POR is to monitor ground-connected switches (current sources are selected). To set an input to monitor supply-connected switches, set the corresponding bit to logic 1.

8.3.8.2 Input Mode Selection

The TIC12400 has a built-in ADC and a comparator that can be used to monitor resistor coded switches or digital switches. Digital switch inputs have only two states, either open or closed, and can be adequately detected by a comparator. Resistor coded switches may have multiple positions that need to be detected, and an ADC is appropriate to monitor the different states. Each input of the TIC12400 can be individually programmed to use either a comparator or an ADC by configuring the appropriate bits in theMODE register depending on the knowledge of the external switch connections. The benefit of using a comparator instead of an ADC to monitor digital switches is its reduced polling time, which translates to overall power saving when the device operates in the low-power polling mode.

Comparator input mode is selected by default for all enabled inputs upon device reset.

8.3.8.3 Input Enable Selection

The TIC12400 provides switch status monitoring for up to 24 inputs, but there might be circumstances in which not all inputs need to be constantly monitored. The microcontroller may choose to enable/disable monitoring of certain inputs by configuring the IN_EN register. Setting the corresponding bit to logic 0 to de-activates the wetting current source/sink and stops switch status monitoring for the input. Disabling monitoring of unused inputs reduce overall power consumption of the device.

All inputs are disabled by default upon device reset.

8.3.8.4 Thresholds Adjustment

When an input is configured as comparator input mode, the threshold level for interrupt generation of can be programmed by setting the THRES_COMP register. The threshold level settings can be set to for each individual input groups and each group consist of 4 inputs. Four threshold levels are available: 2V, 2.7V, 3V, and 4V.

When an input is configured as ADC input mode, the threshold level for interrupt generation can be configured, up to 1023 different levels, by setting the THRES_CFG1 to THRES_CFG2 registers. One threshold level can be programmed individually for each of the input from IN0 to IN11. Additionally, one common threshold, shared between inputs IN0 to IN11, can be programmed by configuring the THRES_COM bits in register MATRIX. The common threshold acts independently from the threshold THRES0 to THRES7. Inputs IN12 to IN17 use 2 preset threshold levels (THRES2A and THRES2B). Inputs 18 to 22 use 3 preset threshold levels (THRES3A, THRES3B, and THRES3C). Input 23 uses 5 preset threshold levels (THRES3A, THRES3B, THRES3C, THRES8 and THRES9).

When multiple threshold settings are used for ADC inputs, the thresholds levels needs to be configured properly. Use the rules below (see Table 2) when setting up the threshold levels:

Caution should be used when setting up the threshold for switches that are connected externally to the supply as there are finite voltage drop (as high as V_{CSI_DROP} for 10mA and 15mA settings) across the current sinks. Therefore, even for an open switch, then voltage on the INx pin can be as high as V_{CSI_DROP} and the detection threshold shall be configured above it. It shall also be noted that a lower wetting current sink setting might not be stronger enough to pull the INx pin close to ground in the presence of a leaky open external switch, as illustrated in the diagram below (see Figure 14). In this example, the external switch, although in the open state, has large leakage current and can be modelled as an equivalent resistor (R_DIRT) of 5kΩ. The 2mA current sink is only able to pull the INx pin voltage down to 2V, even the switch is in the open state.

Figure 14. Example showing The Calculation Of The INx Pin Voltage For A Leaky Supply-connected Switch

It is possible to configure an input to ADC input mode, instead of comparator input mode, to monitor single-threshold digital switches. The following programming procedure is recommended under such configuration:

8.3.8.5 Wetting Current Configuration

There are 6 different wetting current settings (0mA, 1mA, 2mA, 5mA, 10mA, and 15mA) that can be programmed by configuring the WC_CFG0 and WC_CFG1 registers. 0mA is selected by default upon device reset.

To monitor resistor coded switches, a lower wetting current setting (1 mA, 2 mA, or 5 mA) is generally desirable to get the resolution needed to resolve different input voltages while keeping them within the ADC full-scale range (0 V to 6 V). Higher wetting current settings (10mA and 15mA) are useful to clean switch contact oxidation that may form on the surface of an open switch contact. If switch contact cleaning is required for resistor coded switches, the clean current polling (CCP) feature can be activated to generate short cleaning pulses periodically using higher wetting current settings at the end of every polling cycle.

The accuracy of the wetting current has stronger dependency on the V_S voltage when V_S voltage is low. The lower the V_S voltage falls, the more deviation on the wetting currents from their nominal values. Refer to I_{WETT (CSO)} and I_{WETT (CSI)} specifications for more details.

8.3.9.1 INT Pin Assertion Scheme

TIC12400 supports two configurable schemes for INT assertion: static and dynamic. The scheme can be adjusted by configuring the INT_CONFIG bit in the CONFIG register.

If the static INT assertion scheme is used (INT_CONFIG = 0 in the CONFIG register), the INT pin is asserted low upon occurrence of an event. The INT pin is released on the rising edge of CS only if a READ command has been issued to read the INT_STAT register while CS is low, otherwise the INT will be kept low indefinitely. The content of the INT_STAT interrupt register is latched on the first rising edge of SCLK after CS goes low for every SPI transaction, and the content is cleared upon a READ command issued to the INT_STAT register, as illustrated in Figure 16.

Figure 16. Static INT Assertion Scheme

In some system implementation, an edge-triggered based microcontroller might potentially miss the INT assertion if it is configured to the static scheme, especially when the microcontroller is in the process of waking up. To prevent missed INT assertion and improve robustness of the interrupt behavior, the TIC12400 provides the option to use the dynamic assertion scheme for the INT pin. When the dynamic scheme is used (INT_CONFIG= 1 in the CONFIG register), the INT pin is asserted low for a duration of t_{INT_ACTIVE}, and is de-asserted back to high if the INT_STAT register has not been read after t_{INT_ACTIVE} has elapsed. The INT is kept high for a duration of t_{INT_INACTIVE}, and is re-asserted low after t_{INT_INACTIVE} has elapsed. TheINT pin continues to toggle until the INT_STAT register is read.

If the INT_STAT register is read when INT pin is asserted low, the INT pin is released on the READ command’s CS rising edge and the content of the INT_STAT register is also cleared, as shown in Figure 17. If the INT_STAT register is read when INT pin is de-asserted, the content of the INT_STAT register is cleared on the READ command’s CS rising edge, and the INT pin is not re-asserted back low, as shown in Figure 18.

Figure 17. INT Assertion Scheme With INT_STAT Register Read During t_{INT_ACTIVE}

Figure 18. Dynamic INT Assertion Scheme With INT_STAT Register Read During t_{INT_INACTIVE}

The static INT assertion scheme is selected by default upon device reset. The INT pin assertion scheme can only be changed when bit TRIGGER is logic 0 in the CONFIG register.

8.3.9.2 Interrupt Idle Time (t_{INT_IDLE}) Time

Interrupt idle time (t_{INT_IDLE}) is implemented in TIC12400 to:

• Allow the INT pin enough time to be pulled back high by the external pull-up resistor to allow the next assertion to be detectable by an edge-triggered microcontroller.
• Minimize the chance of glitching on the INT pin if back-to-back events occur.

When there is a pending interrupt event and the interrupt event is not masked, t_{INT_IDLE} is applied after the READ command is issued to the INT_STAT register. If another event occurs during the interrupt idle time, the INT_STAT register content is updated instantly, but the INT pin is not asserted low until t_{INT_IDLE} has elapsed. If another READ command is issued to the INT_STAT register during t_{INT_IDLE}, the INT_STAT register content is cleared immediately, but the INT pin is not re-asserted back low after t_{INT_IDLE} has elapsed. An example of the interrupt idle time is given below to illustrate the INT pin behavior under the static /INT assertion schemes:

Figure 19. INT Assertion Scheme With t_{INT_IDLE}

8.3.9.3 Microcontroller Wake-Up

When used together with external PNP transistors, the INT pin could also be used for wake-up purpose to activate a voltage regulator via its inhibit inputs (see Figure 20). This is especially useful for waking up a microcontroller in sleep mode. Before the wake-up, the V_DD could be unavailable to the TIC12400 and the INT pin can be pulled up externally to the V_S voltage. When an event (switch status change, temperature warning, or OV…etc) takes place, the INT pin will be asserted low to activate the voltage regulator, which in turn activates the microcontroller to enable the communication between the microcontroller and the TIC12400. The event information is stored inside the device interrupt register (INT_STAT) for the microcontrollers retrieval when the communication is reestablished.

The wake-up implementation is applicable only when the device is configured to use the static INT assertion scheme.

Figure 20. INT Connection to Support Microcontroller Wake-Up

8.3.9.4 Interrupt Enable/disable And Interrupt generation Conditions

Each switch input can be programmed to enable or disable interrupt generation upon status change by configuring registers INT_EN_COMP1 to INT_EN_COMP2 (for comparator inputs) and INT_EN_CFG1 to INT_EN_CFG4 (for ADC inputs). Interrupt generation condition can be adjusted for THRES_COM (for IN0-IN11) by adjusting the IN_COM_EN bit in the MATRIX register.

The abovementioned registers can also be used to control interrupt generation condition based on the following settings:

1. Rising edge: an interrupt is generated if the current input measurement is above the corresponding threshold and the previous measurement was below.
2. Falling edge: an interrupt is generated if the current input measurement is below the corresponding threshold and the previous measurement was above.
3. Both edges: changes of the input voltage in either direction results in an interrupt generation.

Note interrupt generation from switch status change is disabled for all inputs by default upon device reset.

8.3.9.5 Detection Filter

When monitoring the switch input status, an detection filter can be configured by setting the DET_FILTER bits in the CONFIG register to generate switch status change (SSC) interrupt only if the same input status (w.r.t the threshold) is sampled consecutively. This detection filter can be useful to debounce inputs during switch toggle event. Four different filtering schemes are available:

1. Generate an SSC interrupt if the voltage level at an input crossed its threshold
2. Generate an SSC interrupt if the voltage level at an input crossed its threshold and the status is stable (w.r.t. the threshold) for at least 2 consecutive polling cycles
3. Generate an SSC interrupt if the voltage level at an input crossed its threshold and the status is stable (w.r.t. the threshold) for at least 3 consecutive polling cycles
4. Generate an SSC interrupt if the voltage level at an input crossed its threshold and the status is stable (w.r.t. the threshold) for at least 4 consecutive polling cycles

The default value of switch status is stored internally after the 1st detection cycle, even if detection filter (by configure the DET_FILTER in the CONFIG register) is used. An example is illustrated below with the assumption that DET_FILTER in register CONFIG is set to 11 (SSC interrupt generated if the input crosses threshold and the status is stable w.r.t. the threshold for at least 4 consecutive detection cycles). Assume switch status change is detected in the 3rd detection cycle and stays the same for the next 3 cycles.

Tthe detection filter applies to all enabled inputs regardless its input modes (ADC or comparator) selection. The detection filter counter is reset to 0 when the TRIGGER bit in the CONFIG register is de-asserted to logic 0. Upon device reset, the default setting for the detection filter is set to generating an SSC interrupt at every threshold crossing.

Note the detection filter does not apply to the common threshold THRES_COM.

Table 4. Temperature Monitoring Characteristics of TIC12400

8.3.10.1 Temperature Warning (TW)

When the device temperature goes above the temperature warning trigger temperature (T_TW), the TIC12400 performs the following operations:

1. Generate an interrupt by asserting the INT pin low and flag the TW bit in INT_STAT register to logic 1. The TEMP bit in the SPI flag is also flagged to logic 1 for all SPI transactions.
2. The TW_STAT bit of the IN_STAT_MISC register is flagged to logic 1.
3. If the TW_CUR_DIS_CSO or TW_CUR_DIS_CSO bit in CONFIG register set to logic 0 (default), the wetting current is adjusted down to 2 mA for 10 mA or 15 mA settings. The wetting current stays at its pre-configured value if 0 mA, 1 mA, 2 mA, or 5 mA setting is used.
4. Maintain the low wetting current as long as the device junction temperature stays above T_TW - T_HYS.

The INT pin is released and the INT_STAT register content is cleared on the rising edge of CS provided the INT_STAT register has been read during CS low. The TIC12400 continues to monitor the temperature, but does not issue further interrupts if the temperature continues to stay above T_TW- T_HYS. The status bit TW_STAT in register IN_STAT_MISC continues to stay at logic 1 as long as the temperature warning condition exists.

If desired, the reduction of wetting current down to 2 mA setting (from 10 mA or 15 mA) can be disabled by setting the TW_CUR_DIS_CSO or TW_CUR_DIS_CSI bit in the CONFIG register to 1. The interrupt is still generated (INT asserted low and INT_STAT interrupt register content updated) when the temperature warning event occurs but the wetting current is not reduced. This setting applies to both the polling and continuous mode operation. Note if the feature is enabled, switch detection result might be impacted upon T_TW event if the wetting current is reduced to 2mA from 10mA or 15mA.

When the temperature drops below T_TW - T_HYS, the INT pin is asserted low (if released previously) to notify the microcontroller that the temperature warning condition no longer exists. The TW bit of the interrupt register INT_STAT is flagged logic 1. The TW_STAT bit in the IN_STAT_MISC register is de-asserted back to logic 0. The device resumes operation using the current programmed settings (regardless of the INT and CS status).

8.3.10.2 Temperature Shutdown (TSD)

After the device enters TW condition, if the junction temperature continues to rise and goes above the temperature shutdown threshold (T_TSD), the TIC12400 enters the Temperature Shutdown (TSD) condition and performs the following operations:

1. Opens all the switches connected to the current sources/sinks to prevent any further heating due to excessive current flow.
2. Generate an interrupt by asserting the INT pin (if not already asserted) low and flag the bit TSD in the INT_STAT register to logic 1. The TEMP bit in the SPI flag is also flagged to logic 1 for all SPI transactions.
3. The TSD_STAT bit of the IN_STAT_MISC register is flagged to logic 1. The TW_STAT bit also stays at logic 1.
4. SPI communication stays on, and all register settings say intact without resetting. Previous switch status, if needed, can be retrieved without any interruption.
5. Maintain the setting as long as the junction temperature stays above T_TSD - T_HYS.

The INT pin is released and the INT_STAT register content is cleared on the rising edge of CS provided the INT_STAT register has been read during CS low. The TIC12400 continues to monitor the temperature, but does not issue further interrupts if the temperature continues to stay above T_TSD- T_HYS. The status bit TSD_STAT in register IN_STAT_MISC continues to stay at logic 1 as long as the temperature shutdown condition exists.

When the temperature drops below T_TSD - T_HYS, the INT pin is asserted low (if released previously) to notify the microcontroller that the temperature shutdown condition no longer exists. The TSD bit of the interrupt register INT_STAT is flagged logic 1. In the IN_STAT_MISC register, the TSD_STAT bit is de-asserted back to logic 0, while the TW_STAT bit stays at logic 1. The device resumes operation using the wetting current setting described in section Temperature Warning if the temperature stays above T_TW - T_HYS. Note the polling restarts from the first enabled channel and the SSC interrupt is generated at the end of the first polling cycle. The detected switch status from the first polling cycle becomes the default switch status for subsequent polling.

Table 5. CRC calculation rule

8.4.2.1 Standard Polling

In standard polling mode, wetting current is applied to each input for a pre-programmed polling active time set by the POLL_ACT_TIME bits in the CONFIG register between 64us and 2048 us. At the end of the wetting current application, the input voltage is sampled by the comparator (if input is configured as comparator input mode) or the ADC (if input is configured as ADC input mode). Each input is cycled through in sequential order from IN0 to IN23. Sampling is repeated at a frequency set by the POLL_TIME bits in the CONFIG register from 2ms to 4096ms. Wetting currents are applied to closed switches only during the polling active time; hence the overall system current consumption can be greatly reduced.

Similar to continuous mode, after the first polling cycle, the switch status of each input (below or above detection threshold) is stored internally in registers (IN_STAT_COMP for comparator inputs and IN_STAT_ADC0 to IN_STAT_ADC1 for ADC inputs) to be used as the default state for subsequent polling cycles. The digital values (if the input is configured as ADC input mode) are stored inside the registers ANA_STAT0 toANA_STAT11. The INT pin is asserted low to notify the microcontroller that the default switch status is ready to be read. The SSC bit in INT_STAT register and the SPI status flag SSC are also asserted to logic 1. The INT_STAT register is cleared and /INT pin de-asserted if a SPI READ commanded is issued to the register. Note the interrupt is always generated after the 1st polling cycle (after the TRIGGER bit in register CONFIG is set to logic 1). In subsequent polling cycles, the interrupt is generated only if switch status change is detected.

An example of the timing diagram of the polling mode operation is shown in Figure 23. Note in this example, IN1 is set to comparator input mode, while the other inputs are set to ADC input mode. As a result, the wetting current applied to IN2 is activated faster (t_COMP instead of t_ADC after IN1 wetting current turns off) to shorten the overall polling period. Shortened polling period translates to reduced overall power consumption for the system.

Figure 23. An Example Of The Polling Sequence In Standard Polling Mode

If the switch position changes between two active polling times, no interrupt will be generated and the status registers (IN_STAT_COMP for comparator inputs and IN_STAT_ADC0 to IN_STAT_ADC1 for ADC inputs) will not reflect such a change. An example is shown in Figure 24.

Figure 24. Example For Ignored Switch Position Change Between 2 Wetting Current Cycles

8.4.2.2 Matrix Polling

Figure 25. TIC12400 Matrix Configuration

From IN4 to IN15, a special input switch matrix (see Figure 25) can be configured and monitored in addition to the standard switches to GND and V_SUPPLY. This feature could be useful to monitor a special switch input configuration call Matrix, as required by some specific OEMs.

Three different matrix configurations are possible, and are defined by MATRIX bits in the MATRIX register. If the MATRIX bits are set to ‘00’, all inputs are treated as standard inputs with identical polling active time according to the POLL_ACT_TIME bits in the CONFIG register. Any settings other than ‘00’ for MATRIX bits causes the polling active time for the matrix inputs to be configured according to POLL_ACT_TIME_M bits in the MATRIX register. Inputs that are not part of the matrix configuration will be configured using the POLL_ACT_TIME bits in the CONFIG register. t_{POLL_ACT_TIME_M} should be configured properly to allow sufficient time for the current source/sink to charge/discharge the capacitors (if any) connected to the switch inputs.

The TIC12400 implements a different polling scheme when matrix input is configured. After the polling sequence is started (by setting TRIGGER bit in CONFIG register to logic 1), the polling takes place within the matrix input group first before the rest of the standard inputs are polled. After the matrix inputs are polled, the switch status of each input combination (below or above detection threshold) is stored internally in registers IN_STAT_MATRIX0 and IN_STAT_MATRIX1, and it is used as the default state for subsequent matrix polling cycles. The standard inputs follow the same polling behavior as described in section Standard Polling. After the polling cycle (matrix+ standard) is completed, the INT pin is asserted low to notify the microcontroller that the default switch status is ready to be read. The SSC bit in the INT_STAT register and the SPI status flag SSC are also asserted to logic 1.

The INT_STAT register is cleared and INT pin de-asserted if a SPI READ commanded is issued to the register. Note the interrupt is always generated after the 1st complete polling cycle (after the TRIGGER bit in register CONFIG is set to logic 1). In subsequent polling cycles, the interrupt is generated only if switch status change is detected.

Note the following programming requirement when using the matrix polling:

• It is critical to program the CSO/CSI configuration for each matrix input appropriately according to Table 6 to avoid incorrect switch status detection.
• It is mandatory to set higher wetting current for the sinks (IN4-IN9) than the sources (IN10-IN15). The actual current flowing through the external switches will be the lesser of the two settings. If the same setting is used for both the sink and the source, the detected result might be incorrect. Because of this, 15mA setting shall not be used for the current sources and 1 mA setting shall not be used for the current sinks. Depending on the type of matrix switches, the TIC12400 might require some specific wetting current settings to be able to distinguish between switch open/closed states.
• If TW_CUR_DIS_CSO or TW_CUR_DIS_CSI is set to logic 0 in the CONFIG register, wetting current is reduced to 2 mA for 10 mA and 15 mA settings upon TW event. Since it’s mandatory to have higher wetting current for the sinks (IN4-IN9) than the sources (IN10-IN15) during matrix polling,Table 7 below summarizes the only possible settings if TW event is expected:

If higher wetting current is needed and TW event might be expected, the TW wetting current reduction feature needs to be disabled by setting TW_CUR_DIS_CSO or TW_CUR_DIS_CSI bit in the CONFIG register to 1.

• Only comparator input mode is supported for the matrix polling. Do not program the matrix inputs into ADC input mode. The comparison takes place on the source side (IN10-IN15) since the sink side is pulled to ground. Interrupt generation condition can be set by configuring the INT_EN_COMP1and INT_EN_COMP2 registers for inputs IN10 to IN15.

Some programmability is removed when matrix polling mode is used, as listed below:

• To keep the polling scheme simple, the ability to disable inputs is removed for the matrix inputs. Only 3 configurations (4x4, 5x5, and 6x6) can be used for the matrix polling. Standard inputs outside the matrix input group can still be disabled, if desired.
• Detection filter (by configure the DET_FILTER in the CONFIG register) does not apply to the matrix inputs, but still applies to the standard inputs outside the matrix input group.
• When matrix polling is selected, continuous mode is not available to the standard inputs outside the matrix input group.

Figure 26 illustrates an example of the polling sequence for the 6x6 matrix input configuration:

Figure 26. Polling Scheme for 6x6 Matrix Inputs

Figure 27 illustrates an example of the polling sequence for the 5x5 matrix input configuration. Note the input IN9 and IN15 are included in the standard polling sequence.

Figure 27. Polling Scheme For 5x5 Matrix Inputs

Figure 28 illustrates an example of the polling sequence for the 4x4 matrix input configuration. Note inputs IN8, IN9, IN14, and IN15 are included in the standard polling sequence.

Figure 28. Polling Scheme For 4x4 Matrix Inputs

8.4.3.1 Clean Current Polling (CCP)

To detect resistor coded switches or reduce overall power consumption of the chip, a lower wetting current setting might be desired. However, certain system design requires 10mA or higher cleaning current to clear oxide build-up on the mechanical switch contact surface when the current is applied to closed switches. A special type of polling, called the Clean Current Polling (CCP) can be used for this application.

If CCP is enabled, each polling cycle consists of two wetting current activation steps. The first step uses the wetting current setting configured in the WC_CFG0 and WC_CFG1 registers as in the continuous mode or polling mode. The second step (cleaning cycle) is activated simultaneously for all CCP enabled inputs t_{CCP_TRAN} after the normal polling step of the last enabled input. Interrupt generation and INT pin assertion is not impacted by the clean current pulses.

The wetting current and its active time for the cleaning cycle can be configured in the CCP_CFG0 register. The cleaning cycle can be disabled, if desired, for each individual input by programming the CCP_CFG1 register. CCP is available for both continuous mode and the polling mode. To use the CCP feature, at least one input (standard or matrix) or the V_S measurement has to be enabled.

Note that although CCP can be enabled in Matrix polling mode, it is not an effective way to clean the matrix switch contact, since the current supplied from the TIC12400 is divided and distributed across multiple matrix channels.

Figure 29 illustrates the operation of the CCP when the device is configured to the standard polling mode.

Figure 29. Standard Polling With CCP Enabled

Figure 30 illustrates the operation of the CCP when the device is configured to the continuous mode:

Figure 30. Continue Mode With CCP Enabled

8.4.3.2 Wetting Current Auto-Scaling

The 10 mA and 15 mA wetting current settings are useful to clean oxide build-up on the mechanical switch contact surface when the switch changes state from open to close. After the switch is closed, it might be undesirable to keep the wetting current level at high level if only digital switches are monitored since it results in high current consumption and could potentially heat up the device quickly if multiple inputs are monitored. The wetting current auto-scaling feature help mitigate this issue.

When enabled (AUTO_SCALE_DIS_CSO or AUTO_SCALE_DIS_CSI bit = logic 0 in the WC_CFG1 register), wetting current is reduced to 2 mA from 10 mA or 15 mA setting after switch closure is detected. The threshold used to determine a switch closure is the threshold configured in the THRES_COMP register for inputs configured as comparator input mode. For inputs configured as ADC input mode, the threshold used to determine a switch closure depends on the input number, as described in Table 8 below:

The current reduction takes place N cycles after switch closure is detected on an input, where N depends on the setting of the DET_FILTER bits in the CONFIG register:

• DET_FILTER= 00: wetting current is reduced immediately in the next detection cycle after a closed switch is detected.
• DET_FILTER= 01: wetting current is reduced when a closed switch is detected and the switch status is stable for at least 2 consecutive detection cycles
• DET_FILTER= 10: wetting current is reduced when a closed switch is detected and the switch status is stable for at least 3 consecutive detection cycles
• DET_FILTER= 11: when a closed switch is detected and the switch status is stable for at least 4 consecutive detection cycles

The wetting current is adjusted back to the original setting of 10 mA or 15 mA N cycles after an open switch is detected, where N again depends on the DET_FILTER bit setting in the CONFIG register. Figure 31 depicts the behavior of the wetting current auto-scaling feature.

Figure 31. Wetting Current Auto-scaling Behavior

The wetting current auto-scaling only applies to 10 mA and 15 mA settings and is only available in continuous mode. If AUTO_SCALE_DIS_CSO or AUTO_SCALE_DIS_CSI bit is set to logic 1 in the WC_CFG1 registers, the wetting current stays at its original setting when a closed switch is detected. Power dissipation needs to be closely monitored when wetting current auto-scaling is disabled for multiple inputs as the device could heat up quickly when high wetting current settings are used. If the auto-scaling feature is disabled in continuous mode, total power dissipation can be calculated using Equation 1 below.

Equation 1.

where I_{WETT (TOTOAL)} is the sum of all wetting currents from all input channels. Increase in device junction temperature can be calculated based on P ×R_θJA. The junction temperature has to be limited below T_TSD for proper device operation. An interrupt will be issued when the junction temperature exceeds T_TW or T_TSD. For detailed description of the temperature monitoring, please refer to sections Temperature Warning (TW)and Temperature Shutdown (TSD).

8.4.3.3 V_S Measurement

When the TIC12400 is used to monitor resistor-coded switches, the level of V_S supply voltage becomes very critical. If V_S is not sufficiently high, the device might not have enough headroom to produce accurate wetting currents. This could impact the accuracy of the switch status monitoring. It is imperative for the microcontroller to have knowledge of the V_S voltage on a constant basis in such a case.

Measurement of V_S voltage is a feature in TIC12400 that can be enabled by setting the VS_MEAS_EN bit in register CONFIG to logic 1. If enabled, at the end of every detection/polling cycle, the voltage on the V_S pin is sampled and converted by the ADC to an digital value. The conversion takes one extra t_ADC, and the converted value is recorded in the ANA_STAT12 register.

The V_S measurement supports two different V_S voltage ranges that can be configured by the VS_RATIO bit in the CONFIG register. By default (VS_RATIO = logic 0), the supported V_S voltage range is from 6.5 V to 9 V, and V_S voltage in excess of 9 V results in a saturated ADC raw code of 1023. This setting provides better measurement resolution at lower V_S voltages. When VS_RATIO bit is set to logic 1, the supported V_S voltage range is widened to 6.5V to 30V, and V_S voltage in excess of 30 V results in a saturated ADC raw code of 1023. This setting allows wider measurement range but more coarse measurement resolution. It is important to adjust the detection thresholds accordingly depending on the V_S voltage range configured.

Four different thresholds (VS0_THRES2A/B and VS1_THRES2A/B) can be programmed to have the TIC12400 notify the microcontroller when the V_S voltage crosses the thresholds. The value of these thresholds can be programmed by configuring registers THRES_CFG0 to THRES_CFG3 and the mapping can be programmed by configuring registers THRESMAP_VS0_THRES2A/B and THRESMAP_VS1_THRES2A/B bits in the register THRESMAP_CFG2. When setting the thresholds, follow the rules in Table 9 below:

After the V_S measurement is enabled for the first time, the V_S measurement interrupt is always generated (INT pin is asserted low, and the VS0 or VS1 bit in the INT_STAT register is flagged to logic 1) at the end of the first polling cycle to notify the microcontroller the initial V_S measurement result is ready to be retrieved . The VS0_STAT and VS1_STAT bits from register IN_STAT_MISC indicate the status of the V_S voltage with respect to the thresholds, and the ANA_STAT12 register stores the converted digital value of the V_S voltage. The SPI status flag VS_TH is also asserted to logic 1 during SPI communications. Note the status detected in the first polling cycle becomes the baseline value of comparison for subsequent V_S measurements and the interrupt will be generated only if threshold crossing is detected.

Similar to regular inputs, interrupt generation condition can be programmed by setting the VS_TH0_EN and VS_TH1_EN bits in the INT_EN_CFG4 register to the following settings:

1. Rising edge: an interrupt is generated if the current V_S measurement is above the corresponding threshold and the previous measurement was below.
2. Falling edge: an interrupt is generated if the current V_S measurement is below the corresponding threshold and the previous measurement was above.
3. Both edges: changes of the V_S measurement status in either direction results in an interrupt generation.

Interrupt generation can also be disabled by setting VS_TH0_EN or VS_TH1_EN to logic 0 in register INT_EN_CFG4. Once disabled, V_S voltage crossing does not flag the VS0 or VS1 bit in INT_STAT register and does not assert INT pin low. To only mask the INT pin from assertion (while keeping INT_STAT register updated), configure the VS1_EN and VS0_EN bits in register INT_EN_CFG0 to logic 0.

Note the V_S measurement is only intended to be used as part of switch detection sequence to determine the validity of the switch detection states that are reported by the TIC12400. It is not intended to be used for standalone supply monitoring, such as monitoring cranking voltages, due to the potentially delayed response being part of the polling sequence. The V_S measurement result is accurate for V_S above 6.5V.

By default, the V_S voltage measurement is disabled upon device reset.

8.4.3.4 Wetting Current Diagnostic

When the TIC12400 is used to monitor safety-critical switches, it might be valuable for the microcontroller to have knowledge of the wetting current sources/ sinks operating status. This can be achieved by activating the wetting current diagnostic feature provided for inputs IN0 to IN3. IN0 and IN1 can be diagnosed for defective wetting current sources, while IN2 and IN3 can be diagnosed for failed current sinks.

The wetting current diagnostic feature can be activated by setting the WET_D_INx_EN bits in the CONFIG register to 1 for the desired inputs, where x can be 0, 1, 2, or 3. If activated, the TIC12400 checks the status of the wetting current sources/sinks for the configured input periodically as part of the polling sequence. If the wetting current is determined to be flawed, the TIC12400 pulls the INT pin low to notify the host and flag the WET_DIAG bit in the INT_STAT register to logic 1. The OI bit in the SPI flag is also asserted during SPI transactions. The microcontroller can then read bits IN0_D to IN3_D in register IN_STAT_MISC to learn more information on which wetting current source/sink is defective.

The wetting current diagnostic is not performed for inputs that are disabled (IN_EN_x bit = 0 in the IN_EN register) from polling, even if the feature if activated for those inputs. Also, it is critical to configure the current source/sink appropriately (CSO for IN0/IN1 and CSI for IN2/IN3) and program the input to ADC input mode before activating the wetting current diagnostic feature to avoid false interrupt from generation. The wetting current diagnostic feature can be performed regardless of the states of external switches, and it is available in both continuous mode and the polling mode.

Figure 32 shows an example of the feature carried out in a typical polling sequence. In this example, it can be observed that the wetting current is activated for duration of t_{POLL_ACT}+ t_ADC for each input diagnosed. After IN3 is diagnosed, normal polling sequence resumes and the wetting current is activated for t_{POLL_ACT} for the rest of the inputs. The diagnostic is not executed on input IN2 in this example since it is disabled.

Figure 32. An Example Of The Polling Sequence In Standard Polling Mode With Wetting Current Diagnostic Enabled

8.4.3.5 ADC Self-Diagnostic

In addition to the wetting current diagnostic, another diagnostic feature, the ADC self-diagnostic, can be enabled to monitor the integrity of the internal ADC.

The ADC self-diagnostic feature is activated by setting the ADC_DIAG_T bit in the CONFIG register to logic 1. Once enabled, the TIC12400 periodically sends a test voltage to the ADC. The conversion result is stored in the ADC_SELF_ANA bits in the register ANA_STAT12 and it is compared with a pre-defined code to determine whether the conversion is performed properly. If an error is detected, the TIC12400 pulls the INT pin low to notify the host and flag the ADC_DIAG bit in the INT_STAT to logic 1. The bit ADC_D in register IN_STAT_MISC is updated with the result from the self-diagnostic. The ADC self-diagnostic feature is available in both continuous mode and the polling mode.

8.5.1.1 Chip Select (CS)

The system microcontroller selects the TIC12400 to receive communication using the CS pin. With the CS pin in a logic LOW state, command words may be sent to the TIC12400 via the serial input (SI) pin, and the device information can be retrieved by the microcontroller via the serial output (SO) pin. The falling edge of the CS enables the SO output and latches the content of the interrupt register INT_STAT. The microcontroller may issue a READ command to retrieve information stored in the registers. Rising edge on the CS pin initiates the following operations:

1. Disable the output driver and makes SO high-impedance
2. INT pin is reset to logic HIGH if a READ command to the INT_STAT register was issued during CS = LOW.

To avoid any corrupted data, it is essential the HIGH-to-LOW and LOW-to-HIGH transitions of the CS signal occur only when SCLK is in a logic LOW state. A clean CS signal is needed to ensure no incomplete SPI words are sent to the device. The CS pin should be externally pulled up to VDD by a 10-kΩ resistor.

8.5.1.2 System Clock (SCLK)

The system clock (SCLK) pin clocks the internal shift register of the TIC12400. The SI data is latched into the input shift register on the falling edge of the SCLK signal. The SO pin shifts the device stored information out on the rising edge of SCLK. The SO data is available for the microcontroller to read on the falling edge of SCLK.

False clocking of the shift register must be avoided to ensure validity of data and it is essential the SCLK pin be in a logic LOW state whenever CS makes any transition. Therefore, it is recommended that the SCLK pin gets pulled to a logic LOW state as long as the device is not accessed and CS is in a logic HIGH state. When the CS is in a logic HIGH state, any signal on the SCLK and SI pins will be ignored and the SO pin remains as a high impedance output. Refer to Figure 33 and Figure 34 for examples of typical SPI read and write sequence.

8.5.1.3 Slave In (SI)

The SI pin is used for serial instruction data input. SI information is latched into the input register on the falling edge of the SCLK. To program a complete word, 32 bits of information must be enter into the device. The SPI logic counts the number of bits clocked into the IC and enables data latching only if exactly 32 bits have been clocked in. In case the word length exceeds or does not meet the required length, the SPI_FAIL bit of the INT_STAT register is asserted to logic 1 and the INT pin will be asserted low. The data received is considered invalid. Note the SPI_FAIL bit is not flagged if SCLK is not present.

8.5.1.4 Slave Out (SO)

The SO pin is the output from the internal shift register. The SO pin remains high-impedance until the CS pin transitions to a logic LOW state. The negative transition of CS enables the SO output driver and drive the SO output to the HIGH state (by default). The first positive transition of SCLK makes the status data bit 32 available on the SO pin. Each successive positive clock makes the next status data bit available for the microcontroller to read on the falling edge of SCLK. The SI/SO shifting of the data follows a first-in, first-out scheme, with both input and output words transferring the most significant bit (MSB) first.

8.5.2.1 Read Operation

The Read/Write bit (bit 31) of the SI bus needs to be set to logic 0 for a READ operation. The 6-bits address of the register to be accessed follows next on the SI bus. The content from bit 24 to bit 1 does not represent valid command for a read operation and will be ignored. The LSB (bit 0) is the parity bit used to detect communication errors.

On the SO bus, the status flags will be outputted from the TIC12400, followed by the data content in the register that was requested. The LSB is the parity bit used to detect communication errors.

Note there are several test mode registers (not shown in this ASD) used in the TIC12400 in addition to the normal functional registers, and a READ command to these test registers returns the register content. If a READ command is issued to an invalid register address, the TIC12400 will return all 0’s.

8.5.2.2 Write Operation

The Read/Write bit (bit 31) on the SI bus needs to be set to 1 for a write operation. The 6-bits address of the register to be accessed follows next on the SI bus. Note the register needs to be a writable configuration register, or otherwise, the command will be ignored. The content from bit 24 to bit 1 represents the data to be written to the register. The LSB (bit 0) is the parity bit used to detect communication errors.

On the SO bus, the status flags will be outputted from the TIC12400, followed by the previous data content of the same register being written to. The previous data content of the register is latched after the full register address is decoded in the SI command (after bit 25 is transmitted). The new data will replace the previous data content at the end of the SPI transaction if the SI write is a valid command (valid register address and no SPI/parity error). If the write command is invalid, the new data will be ignored and the previous data content of the register stays. The LSB is the parity bit used to detect communication errors.

Note there are several test mode registers (not shown in this ASD) used in the TIC12400 in addition to the normal functional registers. A WRITE command to these test registers have no effect on the register content, though the register content is returned on the SO output. If a WRITE command is issued to an invalid register address, the SO output would returns all 0’s.

8.5.2.3 Status Flag

The status flags are output from SO during every READ or WRITE SPI transaction to indicate system conditions. These bits do not belong to an actual register, but the content is mirrored from the interrupt register INT_STAT. A READ command executed on the INT_STAT would clear both the bits inside the register and the status flag. The following table describes the information that can be obtained from each SPI status flag:

Table 12. DEVICE_ID Register Field Descriptions

Table 13. INT_STAT Register Field Descriptions

Table 14. CRC Register Field Descriptions

Table 15. IN_STAT_MISC Register Field Descriptions

Table 16. IN_STAT_COMP Register Field Descriptions

Table 17. IN_STAT_ADC0 Register Field Descriptions

Table 18. IN_STAT_ADC1 Register Field Descriptions

Table 19. IN_STAT_MATRIX0 Register Field Descriptions

Table 20. IN_STAT_MATRIX1 Register Field Descriptions

Table 21. ANA_STAT0 Register Field Descriptions

Table 22. ANA_STAT1 Register Field Descriptions

Table 23. ANA_STAT2 Register Field Descriptions

Table 24. ANA_STAT3 Register Field Descriptions

Table 25. ANA_STAT4 Register Field Descriptions

Table 26. ANA_STAT5 Register Field Descriptions

Table 27. ANA_STAT6 Register Field Descriptions

Table 28. ANA_STAT7 Register Field Descriptions

Table 29. ANA_STAT8 Register Field Descriptions

Table 30. ANA_STAT9 Register Field Descriptions

Table 31. ANA_STAT10 Register Field Descriptions

Table 32. ANA_STAT11 Register Field Descriptions

Table 33. ANA_STAT12 Register Field Descriptions

Table 34. CONFIG Register Field Descriptions

Table 35. IN_EN Register Field Descriptions

Table 36. CS_SELECT Register Field Descriptions

Table 37. WC_CFG0 Register Field Descriptions

Table 38. WC_CFG1 Register Field Descriptions

Table 39. CCP_CFG0 Register Field Descriptions

Table 40. CCP_CFG1 Register Field Descriptions