ZHCSQV1C March   2020  – December 2022 TCAN1463-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 说明（续）
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  ESD Ratings - IEC Specifications
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Thermal Information
    6. 7.6  Power Dissipation Ratings
    7. 7.7  Power Supply Characteristics
    8. 7.8  Electrical Characteristics
    9. 7.9  Timing Requirements
    10. 7.10 Switching Characteristics
    11. 7.11 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
      1. 9.1.1 Signal Improvement
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Supply Pins
        1. 9.3.1.1 VSUP Pin
        2. 9.3.1.2 VCC Pin
        3. 9.3.1.3 VIO Pin
      2. 9.3.2 Digital Inputs and Outputs
        1. 9.3.2.1 TXD Pin
        2. 9.3.2.2 RXD Pin
        3. 9.3.2.3 nFAULT Pin
        4. 9.3.2.4 EN Pin
        5. 9.3.2.5 nSTB Pin
        6. 9.3.2.6 INH_MASK Pin
      3. 9.3.3 GND
      4. 9.3.4 INH Pin
      5. 9.3.5 WAKE Pin
      6. 9.3.6 CAN Bus Pins
      7. 9.3.7 Faults
        1. 9.3.7.1 Internal and External Fault Indicators
          1. 9.3.7.1.1 Power-Up (PWRON Flag)
          2. 9.3.7.1.2 Wake-Up Request (WAKERQ Flag)
          3. 9.3.7.1.3 Undervoltage Faults
            1. 9.3.7.1.3.1 Undervoltage on VSUP
            2. 9.3.7.1.3.2 Undervoltage on VCC
            3. 9.3.7.1.3.3 Undervoltage on VIO
          4. 9.3.7.1.4 CAN Bus Fault (CBF Flag)
          5. 9.3.7.1.5 TXD Clamped Low (TXDCLP Flag)
          6. 9.3.7.1.6 TXD Dominant State Timeout (TXDDTO Flag)
          7. 9.3.7.1.7 TXD Shorted to RXD Fault (TXDRXD Flag)
          8. 9.3.7.1.8 CAN Bus Dominant Fault (CANDOM Flag)
      8. 9.3.8 Local Faults
        1. 9.3.8.1 TXD Clamped Low (TXDCLP)
        2. 9.3.8.2 TXD Dominant Timeout (TXD DTO)
        3. 9.3.8.3 Thermal Shutdown (TSD)
        4. 9.3.8.4 Undervoltage Lockout (UVLO)
        5. 9.3.8.5 Unpowered Devices
        6. 9.3.8.6 Floating Terminals
        7. 9.3.8.7 CAN Bus Short-Circuit Current Limiting
    4. 9.4 Device Functional Modes
      1. 9.4.1 Operating Mode Description
        1. 9.4.1.1 Normal Mode
        2. 9.4.1.2 Silent Mode
        3. 9.4.1.3 Standby Mode
        4. 9.4.1.4 Go-To-Sleep Mode
        5. 9.4.1.5 Sleep Mode
          1. 9.4.1.5.1 Remote Wake Request via Wake-Up Pattern (WUP)
          2. 9.4.1.5.2 Local Wake-Up (LWU) via WAKE Input Terminal
      2. 9.4.2 CAN Transceiver
        1. 9.4.2.1 CAN Transceiver Operation
          1. 9.4.2.1.1 CAN Transceiver Modes
            1. 9.4.2.1.1.1 CAN Off Mode
            2. 9.4.2.1.1.2 CAN Autonomous: Inactive and Active
            3. 9.4.2.1.1.3 CAN Active
          2. 9.4.2.1.2 Driver and Receiver Function Tables
          3. 9.4.2.1.3 CAN Bus States
  10. 10Application Information Disclaimer
    1. 10.1 Application Information
      1. 10.1.1 Typical Application
      2. 10.1.2 Design Requirements
        1. 10.1.2.1 Bus Loading, Length and Number of Nodes
      3. 10.1.3 Detailed Design Procedure
        1. 10.1.3.1 CAN Termination
      4. 10.1.4 Application Curves
      5. 10.1.5 Power Supply Recommendations
      6. 10.1.6 Layout
        1. 10.1.6.1 Layout Guidelines
        2. 10.1.6.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
    2. 11.2 接收文档更新通知
    3. 11.3 支持资源
    4. 11.4 商标
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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7.10 Switching Characteristics

Over recommended operating conditions with TJ = -40°C to 150°C, unless otherwise noted. All typical values are taken at 25°C, VSUP = 12 V, VIO = 3.3 V, VCC = 5 V and RL = 60 Ω
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Driver Characteristics
tprop(TxD-busdom) Propagation delay time, high-to-low TXD edge to bus dominant (recessive to dominant)
RL = 60 Ω, CL = 100 pF, RCM = open
See  Figure 8-4		 80 ns
tprop(TxD-busrec) Propagation delay time, low-to-high TXD edge to bus recessive (dominant to recessive) 80 ns
tsk(p) Pulse skew (|tprop(TxD-busdom) - tprop(TxD-busrec)|) RL = 60 Ω, CL = 100 pF, RCM = open
See Figure 8-4		 3 ns
tR Differential output signal rise time 25 ns
tF Differential output signal fall time 25 ns
tTXDDTO Dominant timeout TXD = 0 V, RL = 60 Ω, CL = open
See Figure 8-7		 1.2 3.8 ms
Receiver Characteristics
tprop(busdom-RxD) Propagation delay time, bus dominant input to RxD low output
CL(RXD) = 15 pF
See Figure 8-5		 110 ns
tprop(busrec-RxD) Propagation delay time, bus to recessive input to RXD high output 110 ns
tR Output signal rise time (RXD) CL(RXD) = 15 pF
See Figure 8-5		 3 ns
tF Output signal fall time (RXD) 3 ns
tBUSDOM Dominant time out RL = 60 Ω, CL = open
See Figure 8-5		 1.4 3.8 ms
CAN FD Characteristics
tBIT(BUS)(1) Bit time on CAN bus output pins with tBIT(TXD) = 500 ns RL = 60 Ω, CL1 = open, CL2 = 100 pF, CL(RXD) = 15
ΔtREC = tBIT(RXD) - tBIT(BUS)
See Figure 8-6		 490 510 ns
Bit time on CAN bus output pins with tBIT(TXD) = 200 ns 190 210 ns
Bit time on CAN bus output pins with tBIT(TXD) = 125 ns(2) 115 135 ns
tBIT(RXD)(1) Bit time on RXD output pins with tBIT(TXD) = 500 ns 470 520 ns
Bit time on RXD output pins with tBIT(TXD) = 200 ns 170 210 ns
Bit time on RXD output pins with tBIT(TXD) = 125 ns(2) 95 135 ns
ΔtREC(1) Receiver timing symmetry with tBIT(TXD) = 500 ns –20 15 ns
Receiver timing symmetry with tBIT(TXD) = 200 ns –20 15 ns
Receiver timing symmetry with tBIT(TXD) = 125 ns(3) –20 15 ns
Signal Improvement Characteristics
tSIC_TX_base Signal improvement time TX-based Time from rising edge of the TxD signal to the end of the signal improvement phase 530 ns
ΔtBit(Bus) Transmitted bit width variation Bus recessive bit length variation relative to TxD bit length, see Figure 8-6 ΔtBit(Bus) = tBit(Bus) - tBit(TxD) –10 10 ns
ΔtBIT(RxD) Received bit width variation RxD recessive bit length variation relative to TXD bit length, see Figure 8-6 ΔtBit(RxD) = tBit(RxD) - tBit(TxD) –30 20 ns
ΔtREC Receiver timing symmetry RXD recessive bit length variation relative to bus bit length, see Figure 8-6 ΔtREC = tBit(RxD) - tBit(Bus) –20 15 ns
(1) The input signal on TXD shall have rise times and fall times (10% to 90%) of less than 10 ns
(2) Specified by design and verified via bench characterization