SLVSLJ4 April   2026 TCA9847

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics (Global)
    6. 5.6 I2C Interface Timing Requirements
    7. 5.7 Reset Timing Requirements
    8. 5.8 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 RESET Input
      2. 7.4.2 Power-On Reset
    5. 7.5 Programming
      1. 7.5.1 I2C Interface
      2. 7.5.2 Device Address
      3. 7.5.3 Bus Transactions
        1. 7.5.3.1 Writes
        2. 7.5.3.2 Reads
      4. 7.5.4 Control Register
      5. 7.5.5 RESET Input
      6. 7.5.6 Power-On Reset
      7. 7.5.7 Software Reset
      8. 7.5.8 Device ID
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Voltage Translation Requirements
      2. 8.2.2 Detailed Design Procedure
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power-On Reset Requirements
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information
    2. 11.2 Mechanical Data

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订购信息

8.3.1 Power-On Reset Requirements

In the event of a glitch or data corruption, TCA9847 can be reset to the default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application.

A power-on reset is shown in Figure 8-2.

TCA9847 Power-On Reset Waveform
VCC is Lowered Below the POR Threshold, Then Ramped Back Up to VCC
Figure 8-2 Power-On Reset Waveform

Table 8-1 specifies the performance of the power-on reset feature for TCA9847 for both types of power-on reset.

Table 8-1 Recommended Supply Sequencing and Ramp Rates(1)
PARAMETERMINMAXUNIT
VCC_FTFall timeSee Figure 8-20.12000ms
VCC_RTRise timeSee Figure 8-20.12000ms
VCC_TRRTime to re-ramp (when VCC drops below VPORF(min) – 50mV or when VCC drops to GND)See Figure 8-210μs
VCC_GHLevel that VCC can glitch down to, but not cause a functional disruption when VCC_GW = 1μsSee Figure 8-31V
VCC_GWGlitch width that does not cause a functional disruption when VCC_GH = 0.5 × VCCSee Figure 8-310μs
(1) All supply sequencing and ramp rate values are measured at TA = 25°C

Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and device impedance are factors that affect power-on reset performance. Figure 8-3 and Table 8-1 provide more information on how to measure these specifications.

TCA9847 Glitch Width and Glitch Height Figure 8-3 Glitch Width and Glitch Height

VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and all the registers and the I2C/SMBus state machine are initialized to the default states. The value of VPOR differs based on the VCC being lowered to or from 0. Figure 8-4 and Table 8-1 provide more details on this specification.

TCA9847 VPOR Figure 8-4 VPOR