SLASF33 Data sheet | 德州仪器 TI.com.cn

SLASF33 January 2024 TAC5412-Q1

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RTV|32
- MPQF166B

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slasf33_oa

7.1 Page 0 Registers

Table 7-1 lists the memory-mapped registers for the Page 0 registers. All register offset addresses not listed in Table 7-1 should be considered as reserved locations and the register contents should not be modified.

Table 7-1 PAGE 0 Registers

Address	Acronym	Register Name	Reset Value	Section
0x0	PAGE_CFG	Device page register	0x00	Section 7.1.1
0x1	SW_RESET	Software reset register	0x00	Section 7.1.2
0x2	VREF_CFG		0x00	Section 7.1.3
0x3	AVDD_IOVDD_STS		0x00	Section 7.1.4
0x4	MISC_CFG		0x00	Section 7.1.5
0x5	MISC_CFG1		0x15	Section 7.1.6
0x6	DAC_CFG_A0	DAC DEPOP configuration register	0x55	Section 7.1.7
0x7	MISC_CFG0	Misc. configuration register	0x00	Section 7.1.8
0xA	GPIO1_CFG0	GPIO1 configuration register 0	0x32	Section 7.1.9
0xC	GPO1A_CFG0	GPO1A configuration register 0	0x00	Section 7.1.10
0xD	GPI_CFG	GPI1 configuration register 0	0x00	Section 7.1.11
0xE	GPO_GPI_VAL	GPIO, GPO output value register	0x00	Section 7.1.12
0xF	INTF_CFG0	Interface configuration register 0	0x00	Section 7.1.13
0x10	INTF_CFG1	Interface configuration register 1	0x52	Section 7.1.14
0x11	INTF_CFG2	Interface configuration register 2	0x80	Section 7.1.15
0x12	INTF_CFG3	Interface configuration register 3	0x00	Section 7.1.16
0x13	INTF_CFG4	Interface configuration register 3	0x00	Section 7.1.17
0x14	INTF_CFG5	Interface configuration register 4	0x00	Section 7.1.18
0x15	INTF_CFG6	Interface configuration register 5	0x00	Section 7.1.19
0x18	ASI_CFG0	ASI configuration register 0	0x40	Section 7.1.20
0x19	ASI_CFG1	ASI configuration register 1	0x00	Section 7.1.21
0x1A	PASI_CFG0	Primary ASI configuration register 0	0x30	Section 7.1.22
0x1B	PASI_TX_CFG0	PASI TX configuration register 0	0x00	Section 7.1.23
0x1C	PASI_TX_CFG1	PASI TX configuration register 1	0x00	Section 7.1.24
0x1D	PASI_TX_CFG2	PASI TX configuration register 2	0x00	Section 7.1.25
0x1E	PASI_TX_CH1_CFG	PASI TX Channel 1 configuration register	0x20	Section 7.1.26
0x1F	PASI_TX_CH2_CFG	PASI TX Channel 2 configuration register	0x21	Section 7.1.27
0x20	PASI_TX_CH3_CFG	PASI TX Channel 3 configuration register	0x02	Section 7.1.28
0x21	PASI_TX_CH4_CFG	PASI TX Channel 4 configuration register	0x03	Section 7.1.29
0x22	PASI_TX_CH5_CFG	PASI TX Channel 5 configuration register	0x04	Section 7.1.30
0x23	PASI_TX_CH6_CFG	PASI TX Channel 6 configuration register	0x05	Section 7.1.31
0x24	PASI_TX_CH7_CFG	PASI TX Channel 7 configuration register	0x06	Section 7.1.32
0x25	PASI_TX_CH8_CFG	PASI TX Channel 8 configuration register	0x07	Section 7.1.33
0x26	PASI_RX_CFG0	PASI RX configuration register 0	0x00	Section 7.1.34
0x27	PASI_RX_CFG1	PASI RX configuration register 1	0x00	Section 7.1.35
0x28	PASI_RX_CH1_CFG	PASI RX Channel 1 configuration register	0x20	Section 7.1.36
0x29	PASI_RX_CH2_CFG	PASI RX Channel 2 configuration register	0x21	Section 7.1.37
0x2A	PASI_RX_CH3_CFG	PASI RX Channel 3 configuration register	0x02	Section 7.1.38
0x2B	PASI_RX_CH4_CFG	PASI RX Channel 4 configuration register	0x03	Section 7.1.39
0x2C	PASI_RX_CH5_CFG	PASI RX Channel 5 configuration register	0x04	Section 7.1.40
0x2D	PASI_RX_CH6_CFG	PASI RX Channel 6 configuration register	0x05	Section 7.1.41
0x2E	PASI_RX_CH7_CFG	PASI RX Channel 7 configuration register	0x06	Section 7.1.42
0x2F	PASI_RX_CH8_CFG	PASI RX Channel 8 configuration register	0x07	Section 7.1.43
0x32	CLK_CFG0	Clock configuration register 0	0x00	Section 7.1.44
0x33	CLK_CFG1	Clock configuration register 1	0x00	Section 7.1.45
0x34	CLK_CFG2	Clock configuration register 2	0x40	Section 7.1.46
0x35	CNT_CLK_CFG0	controller mode clock configuration register 0	0x00	Section 7.1.47
0x36	CNT_CLK_CFG1	controller mode clock configuration register 1	0x00	Section 7.1.48
0x37	CNT_CLK_CFG2	controller mode clock configuration register 2	0x20	Section 7.1.49
0x38	CNT_CLK_CFG3	controller mode clock configuration register 3	0x00	Section 7.1.50
0x39	CNT_CLK_CFG4	controller mode clock configuration register 4	0x00	Section 7.1.51
0x3A	CNT_CLK_CFG5	controller mode clock configuration register 5	0x00	Section 7.1.52
0x3B	CNT_CLK_CFG6	controller mode clock configuration register 6	0x00	Section 7.1.53
0x3C	CLK_ERR_STS0	Clock error and status register 0	0x00	Section 7.1.54
0x3D	CLK_ERR_STS1	Clock error and status register 1	0x00	Section 7.1.55
0x3E	CLK_DET_STS0	Clock ratio detection register 0	0x00	Section 7.1.56
0x3F	CLK_DET_STS1	Clock ratio detection register 1	0x00	Section 7.1.57
0x40	CLK_DET_STS2	Clock ratio detection register 2	0x00	Section 7.1.58
0x41	CLK_DET_STS3	Clock ratio detection register 3	0x00	Section 7.1.59
0x42	INT_CFG	Interrupt configuration register	0x00	Section 7.1.60
0x43	DAC_FLT_CFG	Interrupt configuration register	0x50	Section 7.1.61
0x4B	ADC_DAC_MISC_CFG	ADC overload Response configuration register	0x00	Section 7.1.62
0x4D	VREF_CFG	Power tune configuration register 0	0x00	Section 7.1.3
0x4E	PWR_TUNE_CFG0	Power tune configuration register 0	0x00	Section 7.1.63
0x4F	PWR_TUNE_CFG1	Power tune configuration register 1	0x00	Section 7.1.64
0x50	ADC_CH1_CFG0	ADC Channel 1 configuration register 0	0x00	Section 7.1.65
0x52	ADC_CH1_CFG2	ADC Channel 1 configuration register 2	0xA1	Section 7.1.66
0x53	ADC_CH1_CFG3	ADC Channel 1 configuration register 3	0x80	Section 7.1.67
0x54	ADC_CH1_CFG4	ADC Channel 1 configuration register 4	0x00	Section 7.1.68
0x55	ADC_CH2_CFG0	ADC Channel 2 configuration register 0	0x00	Section 7.1.69
0x57	ADC_CH2_CFG2	Channel 2 configuration register 2	0xA1	Section 7.1.70
0x58	ADC_CH2_CFG3	ADC Channel 2 configuration register 3	0x80	Section 7.1.71
0x59	ADC_CH2_CFG4	ADC Channel 2 configuration register 4	0x00	Section 7.1.72
0x5A	ADC_CH3_CFG0	ADC Channel 3 configuration register 0	0x00	Section 7.1.73
0x5B	ADC_CH3_CFG2	ADC Channel 3 configuration register 2	0xA1	Section 7.1.74
0x5C	ADC_CH3_CFG3	ADC Channel 3 configuration register 3	0x80	Section 7.1.75
0x5D	ADC_CH3_CFG4	ADC Channel 3 configuration register 4	0x00	Section 7.1.76
0x5E	ADC_CH4_CFG0	ADC Channel 4 configuration register 0	0x00	Section 7.1.77
0x5F	ADC_CH4_CFG2	Channel 4 configuration register 2	0xA1	Section 7.1.78
0x60	ADC_CH4_CFG3	ADC Channel 4 configuration register 3	0x80	Section 7.1.79
0x61	ADC_CH4_CFG4	ADC Channel 4 configuration register 4	0x00	Section 7.1.80
0x64	OUT1x_CFG0	Channel OUT1x configuration register 0	0x20	Section 7.1.81
0x65	OUT1x_CFG1	Channel OUT1x configuration register 1	0x20	Section 7.1.82
0x66	OUT1x_CFG2	Channel OUT2x configuration register 2	0x20	Section 7.1.83
0x67	DAC_CH1A_CFG0	DAC Channel 1A configuration register 0	0xC9	Section 7.1.84
0x68	DAC_CH1A_CFG1	DAC Channel 1A configuration register 1	0x80	Section 7.1.85
0x69	DAC_CH1B_CFG0	DAC Channel 1B configuration register 0	0xC9	Section 7.1.86
0x6A	DAC_CH1B_CFG1	DAC Channel 1B configuration register 1	0x80	Section 7.1.87
0x6B	OUT2x_CFG0	Channel OUT2x configuration register 0	0x20	Section 7.1.88
0x6C	OUT2x_CFG1	Channel OUT2x configuration register 1	0x20	Section 7.1.89
0x6D	OUT2x_CFG2	Channel OUT2x configuration register 2	0x20	Section 7.1.90
0x6E	DAC_CH2A_CFG0	DAC Channel 2A configuration register 0	0xC9	Section 7.1.91
0x6F	DAC_CH2A_CFG1	DAC Channel 2A configuration register 1	0x80	Section 7.1.92
0x70	DAC_CH2B_CFG0	DAC Channel 2B configuration register 0	0xC9	Section 7.1.93
0x71	DAC_CH2B_CFG1	DAC Channel 2B configuration register 1	0x80	Section 7.1.94
0x72	DSP_CFG0	DSP configuration register 0	0x18	Section 7.1.95
0x73	DSP_CFG1	DSP configuration register 0	0x18	Section 7.1.96
0x76	CH_EN	Channel enable configuration register	0xCC	Section 7.1.97
0x77	DYN_PUPD_CFG	Power up configuration register	0x00	Section 7.1.98
0x78	PWR_CFG	Power up configuration register	0x00	Section 7.1.99
0x79	DEV_STS0	Device status value register 0	0x00	Section 7.1.100
0x7A	DEV_STS1	Device status value register 1	0x80	Section 7.1.101
0x7E	I2C_CKSUM	I²C checksum register	0x00	Section 7.1.102

7.1.1 PAGE_CFG Register (Address = 0x0) [Reset = 0x00]

PAGE_CFG is shown in Figure 7-1 and described in Table 7-2.

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The device memory map is divided into pages. This register sets the page.

Figure 7-1 PAGE_CFG Register

7	6	5	4	3	2	1	0
PAGE[7:0]
R/W-00000000b

Table 7-2 PAGE_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	PAGE[7:0]	R/W	0x0	These bits set the device page. 0d = Page 0 1d = Page 1 2d to 254d = Page 2 to page 254 respectively 255d = Page 255

7.1.2 SW_RESET Register (Address = 0x1) [Reset = 0x00]

SW_RESET is shown in Figure 7-2 and described in Table 7-3.

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This register is the software reset register. Asserting a software reset places all register values in their default power-on-reset (POR) state.

Figure 7-2 SW_RESET Register

7	6	5	4	3	2	1	0
RESERVED							SW_RESET
R-0000000b							R/W-0b

Table 7-3 SW_RESET Register Field Descriptions

Bit	Field	Type	Reset	Description
7-1	RESERVED	R	0x0	Reserved bits; Write only reset value
0	SW_RESET	R/W	0x0	Software reset. This bit is self clearing. 0d = Do not reset 1d = Reset all registers to their reset values

7.1.3 VREF_CFG Register (Address = 0x2) [Reset = 0x00]

VREF_CFG is shown in Figure 7-3 and described in Table 7-4.

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Figure 7-3 VREF_CFG Register

7	6	5	4	3	2	1	0
RESERVED		VREF_QCHG[1:0]		SLEEP_EXIT_VREF_EN	AVDD_MODE	IOVDD_IO_MODE	SLEEP_ENZ
R-00b		R/W-00b		R/W-0b	R/W-0b	R/W-0b	R/W-0b

Table 7-4 VREF_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R	0x0	Reserved bits; Write only reset values
5-4	VREF_QCHG[1:0]	R/W	0x0	The duration of the quick-charge for the VREF external capacitor is set using an internal series impedance of 200 Ω. 0d = VREF quick-charge duration of 3.5 ms (typical) 1d = VREF quick-charge duration of 10 ms (typical) 2d = VREF quick-charge duration of 50 ms (typical) 3d = VREF quick-charge duration of 100 ms (typical)
3	SLEEP_EXIT_VREF_EN	R/W	0x0	Sleep mode exit configuration 0d = Only DREG Enabled 1d = DREG and VREF enabled
2	AVDD_MODE	R/W	0x0	AVDD mode configuration. 0d = Internal AREG regulator is used (Should be used for AVDD > 2V) 1d = AVDD 1.8V used directly for AREG (Strictly use this setting for AVDD 1.7V-1.9V)
1	IOVDD_IO_MODE	R/W	0x0	IOVDD mode configuration. 0d = IOVDD at 3.3V / 1.8V / 1.2V (speed limitation applicable for 1.8V and 1.2V) 1d = IOVDD at 1.8V / 1.2V only (no speed limitation - Strictly don't use this setting for IOVDD > 2V).
0	SLEEP_ENZ	R/W	0x0	Sleep mode setting. 0d = Device is in sleep mode 1d = Device is not in sleep mode

7.1.4 AVDD_IOVDD_STS Register (Address = 0x3) [Reset = 0x00]

AVDD_IOVDD_STS is shown in Figure 7-4 and described in Table 7-5.

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Figure 7-4 AVDD_IOVDD_STS Register

7	6	5	4	3	2	1	0
AVDD_MODE_STS	IOVDD_IO_MODE_STS	RESERVED				BRWNOUT_SHDN_STS	BRWNOUT_SHDN_EXIT_SLEEP
R-0b	R-0b	R-0000b				R-0b	R/W-0b

Table 7-5 AVDD_IOVDD_STS Register Field Descriptions

Bit	Field	Type	Reset	Description
7	AVDD_MODE_STS	R	0x0	AVDD mode status flag register. 0d = AVDD_MODE as per configured 1d = AVDD > 2V (AVDD_MODE forced to 0d)
6	IOVDD_IO_MODE_STS	R	0x0	IOVDD mode status flag register. 0d = IOVDD_MODE as per configured 1d = IOVDD > 2V (IOVDD_IO_MODE forced to 0d)
5-2	RESERVED	R	0x0	Reserved bits; Write only reset values
1	BRWNOUT_SHDN_STS	R	0x0	Brwnout shutdown status 0d = No brwnout shutdown 1d = Brwnout shutdown
0	BRWNOUT_SHDN_EXIT_SLEEP	R/W	0x0	Brwnout shutdown sleep exit config 0d = Stay in sleep mode 1d = Exit sleep mode

7.1.5 MISC_CFG Register (Address = 0x4) [Reset = 0x00]

MISC_CFG is shown in Figure 7-5 and described in Table 7-6.

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Figure 7-5 MISC_CFG Register

7	6	5	4	3	2	1	0
RESERVED	RESERVED	RESERVED	RESERVED	RESERVED	RESERVED	I2C_BRDCAST_EN	RESERVED
R-0b	R-0b	R-0b	R-0b	R-0b	R-0b	R/W-0b	R-0b

Table 7-6 MISC_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0x0	Reserved bit; Write only reset value
6	RESERVED	R	0x0	Reserved bit; Write only reset value
5	RESERVED	R	0x0	Reserved bit; Write only reset value
4	RESERVED	R	0x0	Reserved bit; Write only reset value
3	RESERVED	R	0x0	Reserved bit; Write only reset value
2	RESERVED	R	0x0	Reserved bit; Write only reset value
1	I2C_BRDCAST_EN	R/W	0x0	I²C broadcast addressing setting. 0d = I²C broadcast mode disabled 1d = I²C broadcast mode enabled; the I²C target address is fixed with pin-controlled LSB bits as '0'
0	RESERVED	R	0x0	Reserved bit; Write only reset value

7.1.6 MISC_CFG1 Register (Address = 0x5) [Reset = 0x15]

MISC_CFG1 is shown in Figure 7-6 and described in Table 7-7.

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Figure 7-6 MISC_CFG1 Register

7	6	5	4	3	2	1	0
INCAP_QCHG[1:0]		SHDN_CFG[1:0]		DREG_KA_TIME[1:0]		RESERVED
R/W-00b		R/W-01b		R/W-01b		R-00b

Table 7-7 MISC_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	INCAP_QCHG[1:0]	R/W	0x0	The duration of the quick-charge for the external AC-coupling capacitor is set using an internal series impedance of 800 Ω. 0d = INxP, INxM quick-charge duration of 2.5 ms (typical) 1d = INxP, INxM quick-charge duration of 12.5 ms (typical) 2d = INxP, INxM quick-charge duration of 25 ms (typical) 3d = INxP, INxM quick-charge duration of 50 ms (typical)
5-4	SHDN_CFG[1:0]	R/W	0x1	Shutdown configuration. 0d = DREG is powered down immediately after IOVDD is deasserted 1d = DREG remains active to enable a clean shut down until a time-out(DREG_KA_TIME) is reached; after the time-out period, DREG is forced to power off 2d = DREG remains active until the device cleanly shuts down 3d = Reserved; Don't use
3-2	DREG_KA_TIME[1:0]	R/W	0x1	These bits set how long DREG remains active after IOVDD is deasserted. 0d = DREG remains active for 30 ms (typical) 1d = DREG remains active for 25 ms (typical) 2d = DREG remains active for 10 ms (typical) 3d = DREG remains active for 5 ms (typical)
1-0	RESERVED	R	0x0	Reserved bits; Write only reset values

7.1.7 DAC_CFG_A0 Register (Address = 0x6) [Reset = 0x55]

DAC_CFG_A0 is shown in Figure 7-7 and described in Table 7-8.

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This register configures the device DAC DEPOP

Figure 7-7 DAC_CFG_A0 Register

7	6	5	4	3	2	1	0
RSERIES_DE_POP[3:0]				PWR_UP_TIME_DE_POP[3:0]
R/W-0101b				R/W-0101b

Table 7-8 DAC_CFG_A0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RSERIES_DE_POP[3:0]	R/W	0x5	HP Amp series resistor select config. 0d = Open 1d = 1K 2d = 2.5K 3d = 0.715k 4d = 10K 5d = 0.91k 6d = 2K 7d = 0.667k 8d = 20K Dont use Dont use Dont use Dont use Dont use Dont use Dont use
3-0	PWR_UP_TIME_DE_POP[3:0]	R/W	0x5	HP Amp external cap charging time config. 0d = 2ms 1d = 4ms 2d = 8ms 3d = 16ms 4d = 50ms 5d = 100ms 6d = 250ms 7d = 500ms 8d = 1s 9d = 5s 10d-15d = Reserved

7.1.8 MISC_CFG0 Register (Address = 0x7) [Reset = 0x00]

MISC_CFG0 is shown in Figure 7-8 and described in Table 7-9.

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This register configures the device Misc.

Figure 7-8 MISC_CFG0 Register

7	6	5	4	3	2	1	0
DAC_ST_W_CAP_DIS	DAC_DLYD_PWRUP	DAC_DLYD_PWRUP_TIME	HW_RESET_ON_CLK_STOP_EN	RESERVED
R/W-0b	R/W-0b	R/W-0b	R/W-0b	R-0000b

Table 7-9 MISC_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	DAC_ST_W_CAP_DIS	R/W	0x0	DAC start with dc blocking capacitor discharge sequence. 0d = disable 1d = enable
6	DAC_DLYD_PWRUP	R/W	0x0	DAC power up delayed config. 0d = disable 1d = enable (Delay power-up by based on DAC_DLYD_PWRUP_TIME config)
5	DAC_DLYD_PWRUP_TIME	R/W	0x0	DAC power up delayed time config. 0d = 64-128ms 1d = 256-512ms
4	HW_RESET_ON_CLK_STOP_EN	R/W	0x0	Assertion of Hard Reset when clock selected by CLK_SRC_SEL is not available for 2ms config 0d = disable 1d = enable
3-0	RESERVED	R	0x0	Reserved bits; Write only reset values

7.1.9 GPIO1_CFG0 Register (Address = 0xA) [Reset = 0x32]

GPIO1_CFG0 is shown in Figure 7-9 and described in Table 7-10.

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This register is the GPIO1 configuration register 0.

Figure 7-9 GPIO1_CFG0 Register

7	6	5	4	3	2	1	0
GPIO1_CFG[3:0]				RESERVED	GPIO1_DRV[2:0]
R/W-0011b				R-0b	R/W-010b

Table 7-10 GPIO1_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	GPIO1_CFG[3:0]	R/W	0x3	GPIO1 configuration. 0d = GPIO1 is disabled 1d = GPIO1 is configured as a general-purpose input (GPI) or any other input function 2d = GPIO1 is configured as a general-purpose output (GPO) 3d = GPIO1 is configured as a chip interrupt output (IRQ) 4d = GPIO1 is configured as a PDM clock output (PDMCLK) 5d = GPIO1 is configured as primary ASI DOUT 6d = GPIO1 is configured as primary ASI DOUT2 7d = GPIO1 is configured as secondary ASI DOUT 8d = GPIO1 is configured as secondary ASI DOUT2 9d = GPIO1 is configured as secondary ASI BCLK output 10d = GPIO1 is configured as secondary ASI FSYNC output 11d = GPIO1 is configured as general purpose CLKOUT 12d = GPIO1 is configured as PASI DOUT and SASI DOUT muxed 13d = GPIO1 is configured as DAISY_OUT for DIN Daisy 14d to 15d = Reserved
3	RESERVED	R	0x0	Reserved bit; Write only reset value
2-0	GPIO1_DRV[2:0]	R/W	0x2	GPIO1 output drive configuration. (Not valid if GPIO1_CFG configured as I²S out) 0d = Hi-Z output 1d = Drive active low and active high 2d = Drive active low and weak high 3d = Drive active low and Hi-Z 4d = Drive weak low and active high 5d = Drive Hi-Z and active high 6d to 7d = Reserved; Don't use

7.1.10 GPO1A_CFG0 Register (Address = 0xC) [Reset = 0x00]

GPO1A_CFG0 is shown in Figure 7-10 and described in Table 7-11.

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This register is the GPO1 configuration register 0.

Figure 7-10 GPO1A_CFG0 Register

7	6	5	4	3	2	1	0
GPO1A_CFG[3:0]				SPI_POCI_CFG	GPO1A_DRV[2:0]
R/W-0000b				R/W-0b	R/W-000b

Table 7-11 GPO1A_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	GPO1A_CFG[3:0]	R/W	0x0	GPO1A configuration.(Max frequency is limited to 6MHz. For SPI mode, this pin act as POCI and the below configuration settings are not applicable) (Buskeeper en is not supported when used as DOUT) 0d = GPO1A is disabled 1d = GPO1A is configured as a general-purpose input (GPI) or any other input function 2d = GPO1A is configured as a general-purpose output (GPO) 3d = GPO1A is configured as a chip interrupt output (IRQ) 4d = GPO1A is configured as a PDM clock output (PDMCLK) 5d = GPO1A is configured as primary ASI DOUT 6d = GPO1A is configured as primary ASI DOUT2 7d = GPO1A is configured as secondary ASI DOUT 8d = GPO1A is configured as secondary ASI DOUT2 9d = GPO1A is configured as secondary ASI BCLK output 10d = GPO1A is configured as secondary ASI FSYNC output 11d = GPO1A is configured as general purpose CLKOUT 12d = GPO1A is configured as PASI DOUT and SASI DOUT muxed 13d = GPO1A is configured as DAISY_OUT for DIN Daisy 14d to 15d = Reserved
3	SPI_POCI_CFG	R/W	0x0	SPI POCI configuration. 0d = GPO1A pin act as SPI POCI output (max frequency limited to 6MHz) and GPO1A_CFG and GPO1A_DRV settings are ignored. 0d = GPIO1A pin act as SPI POCI output for high speed use case and GPIO1A_CFG and GPIO1A_DRV settings are ignored.
2-0	GPO1A_DRV[2:0]	R/W	0x0	GPO1A output drive configuration. (Not valid if GPO1A_CFG configured as I²S out) (This is GPO1A in Auto-device but max frequency is limited to 6MHz. For SPI mode, this pin act as SSZ and the below configuration settings are not applicable) 0d = Hi-Z output 1d = Drive active low and active high 2d = Drive active low and weak high 3d = Drive active low and Hi-Z 4d = Drive weak low and active high 5d = Drive Hi-Z and active high 6d to 7d = Reserved; Don't use

7.1.11 GPI_CFG Register (Address = 0xD) [Reset = 0x00]

GPI_CFG is shown in Figure 7-11 and described in Table 7-12.

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This register is the GPI1 configuration register 0.

Figure 7-11 GPI_CFG Register

7	6	5	4	3	2	1	0
RESERVED						GPI1A_CFG	GPI2A_CFG
R-000000b						R/W-0b	R/W-0b

Table 7-12 GPI_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7-2	RESERVED	R	0x0	Reserved bits; Write only reset values
1	GPI1A_CFG	R/W	0x0	GPI1A configuration. 0d = GPI1A is disabled 1d = GPI1A is configured as a general-purpose input (GPI) or any other input function
0	GPI2A_CFG	R/W	0x0	GPI2A configuration. 0d = GPI2A is disabled 1d = GPI2A is configured as a general-purpose input (GPI) or any other input function

7.1.12 GPO_GPI_VAL Register (Address = 0xE) [Reset = 0x00]

GPO_GPI_VAL is shown in Figure 7-12 and described in Table 7-13.

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This register is the GPIO and GPO output value register.

Figure 7-12 GPO_GPI_VAL Register

7	6	5	4	3	2	1	0
GPIO1_VAL	RESERVED	GPO1A_VAL	RESERVED	GPIO1_MON	GPI2A_MON	GPI1A_MON	RESERVED
R/W-0b	R-0b	R/W-0b	R-0b	R-0b	R-0b	R-0b	R-0b

Table 7-13 GPO_GPI_VAL Register Field Descriptions

Bit	Field	Type	Reset	Description
7	GPIO1_VAL	R/W	0x0	GPIO1 output value when configured as a GPO. 0d = Drive the output with a value of 0 1d = Drive the output with a value of 1
6	RESERVED	R	0x0	Reserved bit; Write only reset value
5	GPO1A_VAL	R/W	0x0	GPO1A output value when configured as a GPO. 0d = Drive the output with a value of 0 1d = Drive the output with a value of 1
4	RESERVED	R	0x0	Reserved bit; Write only reset value
3	GPIO1_MON	R	0x0	GPIO1 monitor value when configured as a GPI. 0d = Input monitor value 0 1d = Input monitor value 1
2	GPI2A_MON	R	0x0	GPI2A monitor value when configured as a GPI. 0d = Input monitor value 0 1d = Input monitor value 1
1	GPI1A_MON	R	0x0	GPI1A monitor value when configured as a GPI. 0d = Input monitor value 0 1d = Input monitor value 1
0	RESERVED	R	0x0	Reserved bit; Write only reset value

7.1.13 INTF_CFG0 Register (Address = 0xF) [Reset = 0x00]

INTF_CFG0 is shown in Figure 7-13 and described in Table 7-14.

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This register is the interface configuration register 0.

Figure 7-13 INTF_CFG0 Register

7	6	5	4	3	2	1	0
RESERVED	CCLK_SEL[1:0]		PASI_DIN2_SEL[2:0]			PASI_BCLK_SEL	PASI_FSYNC_SEL
R-0b	R/W-00b		R/W-000b			R/W-0b	R/W-0b

Table 7-14 INTF_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0x0	Reserved bit; Write only reset value
6-5	CCLK_SEL[1:0]	R/W	0x0	CCLK select configuration. 0d = cclk is disabled 1d = GPIO1 2d = GPI2A 3d = GPI1A
4-2	PASI_DIN2_SEL[2:0]	R/W	0x0	Primary ASI DIN2 select configuration. 0d = Primary ASI DIN2 is disabled 1d = GPIO1 2d = GPI2A 3d = GPI1A 4d = DOUT 5d = Primary ASI DIN 6d to 7d = Reserved
1	PASI_BCLK_SEL	R/W	0x0	Primary ASI BCLK select configuration. 0d = Primary ASI BCLK is BCLK 1d = Primary ASI BCLK is Secondary ASI BCLK
0	PASI_FSYNC_SEL	R/W	0x0	Primary ASI FSYNC select configuration. 0d = Primary ASI FSYNC is FSYNC 1d = Primary ASI FSYNC is Secondary ASI FSYNC

7.1.14 INTF_CFG1 Register (Address = 0x10) [Reset = 0x52]

INTF_CFG1 is shown in Figure 7-14 and described in Table 7-15.

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This register is the interface configuration register 1.

Figure 7-14 INTF_CFG1 Register

7	6	5	4	3	2	1	0
DOUT_SEL[3:0]				DOUT_VAL	DOUT_DRV[2:0]
R/W-0101b				R/W-0b	R/W-010b

Table 7-15 INTF_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	DOUT_SEL[3:0]	R/W	0x5	DOUT select configuration. 0d = DOUT is disabled 1d = DOUT is configured as input 2d = DOUT is configured as a general-purpose output (GPO) 3d = DOUT is configured as a chip interrupt output (IRQ) 4d = DOUT is configured as a PDM clock output (PDMCLK) 5d = DOUT is configured as primary ASI DOUT 6d = DOUT is configured as primary ASI DOUT2 7d = DOUT is configured as secondary ASI DOUT 8d = DOUT is configured as secondary ASI DOUT2 9d = DOUT is configured as secondary ASI BCLK output 10d = DOUT is configured as secondary ASI FSYNC output 11d = DOUT is configured as general purpose CLKOUT 12d = DOUT is configured as PASI DOUT and SASI DOUT muxed 13d = DOUT is configured as DAISY_OUT for DIN Daisy 14d = DOUT is configured as DIN(LOOPBACK) 15d = Reserved
3	DOUT_VAL	R/W	0x0	DOUT output value when configured as a GPO. 0d = Drive the output with a value of 0 1d = Drive the output with a value of 1
2-0	DOUT_DRV[2:0]	R/W	0x2	DOUT output drive configuration. 0d = Hi-Z output 1d = Drive active low and active high 2d = Drive active low and weak high 3d = Drive active low and Hi-Z 4d = Drive weak low and active high 5d = Drive Hi-Z and active high 6d to 7d = Reserved; Don't use

7.1.15 INTF_CFG2 Register (Address = 0x11) [Reset = 0x80]

INTF_CFG2 is shown in Figure 7-15 and described in Table 7-16.

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This register is the interface configuration register 2.

Figure 7-15 INTF_CFG2 Register

7	6	5	4	3	2	1	0
PASI_DIN_EN	SASI_FSYNC_SEL[2:0]			SASI_BCLK_SEL[2:0]			RESERVED
R/W-1b	R/W-000b			R/W-000b			R-0b

Table 7-16 INTF_CFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	PASI_DIN_EN	R/W	0x1	Primary ASI DIN enable configuration. 0d = Primary ASI DIN is disabled 1d = Primary ASI DIN is enabled
6-4	SASI_FSYNC_SEL[2:0]	R/W	0x0	Secondary ASI FSYNC select configuration. 0d = Secondary ASI disabled 1d = GPIO1 2d = GPI2A 3d = GPI1A 4d = Reserved 5d = Primary ASI FSYNC 6d to 7d = Reserved
3-1	SASI_BCLK_SEL[2:0]	R/W	0x0	Secondary ASI BCLK select configuration. 0d = Secondary ASI disabled 1d = GPIO1 2d = GPI2A 3d = GPI1A 4d = Reserved 5d = Primary ASI BCLK 6d to 7d = Reserved
0	RESERVED	R	0x0	Reserved bit; Write only reset value

7.1.16 INTF_CFG3 Register (Address = 0x12) [Reset = 0x00]

INTF_CFG3 is shown in Figure 7-16 and described in Table 7-17.

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This register is the interface configuration register 3.

Figure 7-16 INTF_CFG3 Register

7	6	5	4	3	2	1	0
SASI_DIN_SEL[2:0]			SASI_DIN2_SEL[2:0]			RESERVED
R/W-000b			R/W-000b			R-00b

Table 7-17 INTF_CFG3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-5	SASI_DIN_SEL[2:0]	R/W	0x0	Secondary ASI DIN select configuration. 0d = Seondary ASI DIN is disabled 1d = GPIO1 2d = GPI2A 3d = GPI1A 4d = DOUT 5d = Primary ASI DIN 6d to 7d = Reserved
4-2	SASI_DIN2_SEL[2:0]	R/W	0x0	Seondary ASI DIN2 select configuration. 0d = Seondary ASI DIN2 is disabled 1d = GPIO1 2d = GPI2A 3d = GPI1A 4d = DOUT 5d = Primary ASI DIN 6d to 7d = Reserved
1-0	RESERVED	R	0x0	Reserved bits; Write only reset values

7.1.17 INTF_CFG4 Register (Address = 0x13) [Reset = 0x00]

INTF_CFG4 is shown in Figure 7-17 and described in Table 7-18.

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This register is the interface configuration register 3.

Figure 7-17 INTF_CFG4 Register

7	6	5	4	3	2	1	0
PDM_CH1_SEL	PDM_CH2_SEL	PDMDIN1_EDGE	PDMDIN2_EDGE	PDM_DIN1_SEL[1:0]		PDM_DIN2_SEL[1:0]
R/W-0b	R/W-0b	R/W-0b	R/W-0b	R/W-00b		R/W-00b

Table 7-18 INTF_CFG4 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	PDM_CH1_SEL	R/W	0x0	PDM select configuration for channel 1 of record path. 0d = Channel 1 is analog (ADC) type on the record path 1d = Channel 1 is digital (PDM) type on the record path
6	PDM_CH2_SEL	R/W	0x0	PDM select configuration for channel 2 of record path. 0d = Channel 2 is analog (ADC) type on the record path 1d = Channel 2 is digital (PDM) type on the record path
5	PDMDIN1_EDGE	R/W	0x0	PDMCLK latching edge used for channel 1 and channel 2 data. 0d = Channel 1 data are latched on the negative edge, channel 2 data are latched on the positive edge 1d = Channel 1 data are latched on the positive edge, channel 2 data are latched on the negative edge
4	PDMDIN2_EDGE	R/W	0x0	PDMCLK latching edge used for channel 3 and channel 4 data. 0d = Channel 3 data are latched on the negative edge, channel 4 data are latched on the positive edge 1d = Channel 3 data are latched on the positive edge, channel 4 data are latched on the negative edge
3-2	PDM_DIN1_SEL[1:0]	R/W	0x0	PDM data channels 1 and 2 select configuration. 0d = PDM data channels 1 and 2 are disabled 1d = GPIO1 2d = GPI2A 3d = GPI1A
1-0	PDM_DIN2_SEL[1:0]	R/W	0x0	PDM data channels 3 and 4 select configuration. 0d = PDM data channels 3 and 4 are disabled 1d = GPIO1 2d = GPI2A 3d = GPI1A

7.1.18 INTF_CFG5 Register (Address = 0x14) [Reset = 0x00]

INTF_CFG5 is shown in Figure 7-18 and described in Table 7-19.

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This register is the interface configuration register 4.

Figure 7-18 INTF_CFG5 Register

7	6	5	4	3	2	1	0
PDM_DIN_SEL_OVRD	DOUT_WITH_DIN	PD_ADC_GPIO[1:0]		PD_DAC_GPIO[1:0]		PLIM_GPIO	GPA_GPIO
R/W-0b	R/W-0b	R/W-00b		R/W-00b		R/W-0b	R/W-0b

Table 7-19 INTF_CFG5 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	PDM_DIN_SEL_OVRD	R/W	0x0	PDM data channels (1 and 2)/(3 and 4) select configuration override. 0d = No Override 1d = PDM_DIN1/2_SEL if configured as GPI1 will be overriden as DIN
6	DOUT_WITH_DIN	R/W	0x0	DOUT used as both ASI OUT and ASI IN 0d = DOUT based on DOUT_SEL 1d = DOUT used as both ASI OUT and ASI DIN
5-4	PD_ADC_GPIO[1:0]	R/W	0x0	Power down ADC using GPIO select configuration.(ADC powered down if any one of the PD_ADC_GPIO/ADC_PDZ is configured power down) 0d = Power down ADC using GPIO is disabled 1d = Power down ADC using GPIO1 2d = Power down ADC using GPI2A 3d = Power down ADC using GPI1A
3-2	PD_DAC_GPIO[1:0]	R/W	0x0	Power down DAC using GPIO select configuration.(DAC powered down if any one of the PD_DAC_GPIO/DAC_PDZ is configured power down) 0d = Power down DAC using GPIO is disabled 1d = Power down DAC using GPIO1 2d = Power down DAC using GPI2A 3d = Power down DAC using GPI1A
1	PLIM_GPIO	R/W	0x0	PLIM using GPIO1 configuration. 0d = PLIM using GPIO1 is disabled 1d = PLIM using GPIO1
0	GPA_GPIO	R/W	0x0	GPA using GPIO1 configuration. 0d = GPA using GPIO1 is disabled 1d = GPA using GPIO1

7.1.19 INTF_CFG6 Register (Address = 0x15) [Reset = 0x00]

INTF_CFG6 is shown in Figure 7-19 and described in Table 7-20.

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This register is the interface configuration register 5.

Figure 7-19 INTF_CFG6 Register

7	6	5	4	3	2	1	0
EN_MBIAS_GPIO[1:0]		IADC_CONVST_GPIO[1:0]		RESERVED
R/W-00b		R/W-00b		R-0000b

Table 7-20 INTF_CFG6 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	EN_MBIAS_GPIO[1:0]	R/W	0x0	Enable MICBIAS using GPIO select configuration. 0d = Enable MICBIAS using GPIO is disabled 1d = Enable MICBIAS using GPIO1 2d = Enable MICBIAS using GPI2A 3d = Enable MICBIAS using GPI1A
5-4	IADC_CONVST_GPIO[1:0]	R/W	0x0	IADC conversion start using GPIO select configuration. 0d = Enable IADC using GPIO is disabled 1d = Enable IADC using GPIO1 2d = Enable IADC using GPI2A 3d = Enable IADC using GPI1A
3-0	RESERVED	R	0x0	Reserved bits; Write only reset value

7.1.20 ASI_CFG0 Register (Address = 0x18) [Reset = 0x40]

ASI_CFG0 is shown in Figure 7-20 and described in Table 7-21.

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This register is the ASI configuration register 0.

Figure 7-20 ASI_CFG0 Register

7	6	5	4	3	2	1	0
PASI_DIS	SASI_DIS	SASI_CFG_GANG	DAISY_EN[1:0]		DAISY_IN_SEL[2:0]
R/W-0b	R/W-1b	R/W-0b	R/W-00b		R/W-000b

Table 7-21 ASI_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	PASI_DIS	R/W	0x0	Disable or enable primary ASI (PASI). 0d = Primary ASI enabled 1d = Primary ASI disabled
6	SASI_DIS	R/W	0x1	Disable or enable secondary ASI (SASI). 0d = Secondary ASI enabled 1d = Secondary ASI disabled
5	SASI_CFG_GANG	R/W	0x0	All configurations of secondary ASI ganged with primary ASI. 0d = Secondary ASI has independent configurations 1d = Secondary ASI configurations same as primary ASI
4-3	DAISY_EN[1:0]	R/W	0x0	Daisy chain feature enable (Daisy buffer length is 64, only 1 ASI with 1 DOUT AND DIN available) 0d = Daisy chain disabled 1d = PASI daisy chain enabled (Secondary ASI not available) 2d = SASI daisy chain enabled (Primary ASI not available) 3d = Reserved; Don't use
2-0	DAISY_IN_SEL[2:0]	R/W	0x0	Daisy input select configuration. 0d = Daisy input disabled 1d = GPIO1 2d = GPI2A 3d = GPI1A 4d = Reserved 5d = DIN 6d to 7d = Reserved

7.1.21 ASI_CFG1 Register (Address = 0x19) [Reset = 0x00]

ASI_CFG1 is shown in Figure 7-21 and described in Table 7-22.

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This register is the ASI configuration register 1.

Figure 7-21 ASI_CFG1 Register

7	6	5	4	3	2	1	0
ASI_DOUT_CFG[1:0]		ASI_DIN_CFG[1:0]		DAISY_DIR	RESERVED	RESERVED	RESERVED
R/W-00b		R/W-00b		R/W-0b	R-0b	R-0b	R-0b

Table 7-22 ASI_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	ASI_DOUT_CFG[1:0]	R/W	0x0	ASI data output configuration. 0d = 1 data output for Primary ASI and 1 data output for Secondary ASI 1d = 2 data outputs for Primary ASI 2d = 2 data outputs for Secondary ASI 3d = Reserved; Don't use
5-4	ASI_DIN_CFG[1:0]	R/W	0x0	ASI data input configuration. 0d = 1 data input for Primary ASI and 1 data input for Secondary ASI 1d = 2 data inputs for Primary ASI 2d = 2 data inputs for Secondary ASI 3d = Reserved; Don't use
3	DAISY_DIR	R/W	0x0	Daisy direction configuration. 0d = ASI DOUT daisy 1d = ASI DIN daisy
2	RESERVED	R	0x0	Reserved bit; Write only reset value
1	RESERVED	R	0x0	Reserved bit; Write only reset value
0	RESERVED	R	0x0	Reserved bit; Write only reset value

7.1.22 PASI_CFG0 Register (Address = 0x1A) [Reset = 0x30]

PASI_CFG0 is shown in Figure 7-22 and described in Table 7-23.

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This register is the ASI configuration register 0.

Figure 7-22 PASI_CFG0 Register

7	6	5	4	3	2	1	0
PASI_FORMAT[1:0]		PASI_WLEN[1:0]		PASI_FSYNC_POL	PASI_BCLK_POL	PASI_BUS_ERR	PASI_BUS_ERR_RCOV
R/W-00b		R/W-11b		R/W-0b	R/W-0b	R/W-0b	R/W-0b

Table 7-23 PASI_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	PASI_FORMAT[1:0]	R/W	0x0	Primary ASI protocol format. 0d = TDM mode 1d = I²S mode 2d = LJ (left-justified) mode 3d = Reserved; Don't use
5-4	PASI_WLEN[1:0]	R/W	0x3	Primary ASI word or slot length. 0d = 16 bits (Recommended this setting to be used with 10-kΩ input impedance configuration) 1d = 20 bits 2d = 24 bits 3d = 32 bits
3	PASI_FSYNC_POL	R/W	0x0	ASI FSYNC polarity (for PASI protocol only). 0d = Default polarity as per standard protocol 1d = Inverted polarity with respect to standard protocol
2	PASI_BCLK_POL	R/W	0x0	ASI BCLK polarity (for PASI protocol only). 0d = Default polarity as per standard protocol 1d = Inverted polarity with respect to standard protocol
1	PASI_BUS_ERR	R/W	0x0	ASI bus error detection. 0d = Enable bus error detection 1d = Disable bus error detection
0	PASI_BUS_ERR_RCOV	R/W	0x0	ASI bus error auto resume. 0d = Enable auto resume after bus error recovery 1d = Disable auto resume after bus error recovery and remain powered down until host configures the device

7.1.23 PASI_TX_CFG0 Register (Address = 0x1B) [Reset = 0x00]

PASI_TX_CFG0 is shown in Figure 7-23 and described in Table 7-24.

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This register is the PASI TX configuration register 0.

Figure 7-23 PASI_TX_CFG0 Register

7	6	5	4	3	2	1	0
PASI_TX_EDGE	PASI_TX_FILL	PASI_TX_LSB	PASI_TX_KEEPER[1:0]		PASI_TX_USE_INT_FSYNC	PASI_TX_USE_INT_BCLK	PASI_TDM_PULSE_WIDTH
R/W-0b	R/W-0b	R/W-0b	R/W-00b		R/W-0b	R/W-0b	R/W-0b

Table 7-24 PASI_TX_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	PASI_TX_EDGE	R/W	0x0	Primary ASI data output (on the primary and secondary data pin) transmit edge. 0d = Default edge as per the protocol configuration setting in PASI_BCLK_POL 1d = Inverted following edge (half cycle delay) with respect to the default edge setting
6	PASI_TX_FILL	R/W	0x0	Primary ASI data output (on the primary and secondary data pin) for any unused cycles 0d = Always transmit 0 for unused cycles 1d = Always use Hi-Z for unused cycles
5	PASI_TX_LSB	R/W	0x0	Primary ASI data output (on the primary and secondary data pin) for LSB transmissions. 0d = Transmit the LSB for a full cycle 1d = Transmit the LSB for the first half cycle and Hi-Z for the second half cycle
4-3	PASI_TX_KEEPER[1:0]	R/W	0x0	Primary ASI data output (on the primary and secondary data pin) bus keeper. 0d = Bus keeper is always disabled 1d = Bus keeper is always enabled 2d = Bus keeper is enabled during LSB transmissions only for one cycle 3d = Bus keeper is enabled during LSB transmissions only for one and half cycles
2	PASI_TX_USE_INT_FSYNC	R/W	0x0	Primary ASI uses internal FSYNC for output data generation in Controller mode configuration as applicable. 0d = Use external FSYNC for ASI protocol data generation 1d = Use internal FSYNC for ASI protocol data generation
1	PASI_TX_USE_INT_BCLK	R/W	0x0	Primary ASI uses internal BCLK for output data generation in Controller mode configuration. 0d = Use external BCLK for ASI protocol data generation 1d = Use internal BCLK for ASI protocol data generation
0	PASI_TDM_PULSE_WIDTH	R/W	0x0	Primary ASI fsync pulse width in TDM format. (Valid for Controller mode) 0d = Fsync pulse is 1 bclk period wide 1d = Fsync pulse is 2 bclk period wide

7.1.24 PASI_TX_CFG1 Register (Address = 0x1C) [Reset = 0x00]

PASI_TX_CFG1 is shown in Figure 7-24 and described in Table 7-25.

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This register is the PASI TX configuration register 1.

Figure 7-24 PASI_TX_CFG1 Register

7	6	5	4	3	2	1	0
RESERVED			PASI_TX_OFFSET[4:0]
R-000b			R/W-00000b

Table 7-25 PASI_TX_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-5	RESERVED	R	0x0	Reserved bits; Write only reset values
4-0	PASI_TX_OFFSET[4:0]	R/W	0x0	Primary ASI output data MSB slot 0 offset (on the primary and secondary data pin). 0d = ASI data MSB location has no offset and is as per standard protocol 1d = ASI data MSB location (TDM mode is slot 0 or I²S, LJ mode is the left and right slot 0) offset of one BCLK cycle with respect to standard protocol 2d = ASI data MSB location (TDM mode is slot 0 or I²S, LJ mode is the left and right slot 0) offset of two BCLK cycles with respect to standard protocol 3d to 30d = ASI data MSB location (TDM mode is slot 0 or I²S, LJ mode is the left and right slot 0) offset assigned as per configuration 31d = ASI data MSB location (TDM mode is slot 0 or I²S, LJ mode is the left and right slot 0) offset of 31 BCLK cycles with respect to standard protocol

7.1.25 PASI_TX_CFG2 Register (Address = 0x1D) [Reset = 0x00]

PASI_TX_CFG2 is shown in Figure 7-25 and described in Table 7-26.

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This register is the PASI TX configuration register 2.

Figure 7-25 PASI_TX_CFG2 Register

7	6	5	4	3	2	1	0
PASI_TX_CH8_SEL	PASI_TX_CH7_SEL	PASI_TX_CH6_SEL	PASI_TX_CH5_SEL	PASI_TX_CH4_SEL	PASI_TX_CH3_SEL	PASI_TX_CH2_SEL	PASI_TX_CH1_SEL
R/W-0b	R/W-0b	R/W-0b	R/W-0b	R/W-0b	R/W-0b	R/W-0b	R/W-0b

Table 7-26 PASI_TX_CFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	PASI_TX_CH8_SEL	R/W	0x0	Primary ASI output channel 8 select. 0d = Primary ASI channel 8 output is on DOUT 1d = Primary ASI channel 8 output is on DOUT2
6	PASI_TX_CH7_SEL	R/W	0x0	Primary ASI output channel 7 select. 0d = Primary ASI channel 7 output is on DOUT 1d = Primary ASI channel 7 output is on DOUT2
5	PASI_TX_CH6_SEL	R/W	0x0	Primary ASI output channel 6 select. 0d = Primary ASI channel 6 output is on DOUT 1d = Primary ASI channel 6 output is on DOUT2
4	PASI_TX_CH5_SEL	R/W	0x0	Primary ASI output channel 5 select. 0d = Primary ASI channel 5 output is on DOUT 1d = Primary ASI channel 5 output is on DOUT2
3	PASI_TX_CH4_SEL	R/W	0x0	Primary ASI output channel 4 select. 0d = Primary ASI channel 4 output is on DOUT 1d = Primary ASI channel 4 output is on DOUT2
2	PASI_TX_CH3_SEL	R/W	0x0	Primary ASI output channel 3 select. 0d = Primary ASI channel 3 output is on DOUT 1d = Primary ASI channel 3 output is on DOUT2
1	PASI_TX_CH2_SEL	R/W	0x0	Primary ASI output channel 2 select. 0d = Primary ASI channel 2 output is on DOUT 1d = Primary ASI channel 2 output is on DOUT2
0	PASI_TX_CH1_SEL	R/W	0x0	Primary ASI output channel 1 select. 0d = Primary ASI channel 1 output is on DOUT 1d = Primary ASI channel 1 output is on DOUT2

7.1.26 PASI_TX_CH1_CFG Register (Address = 0x1E) [Reset = 0x20]

PASI_TX_CH1_CFG is shown in Figure 7-26 and described in Table 7-27.

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This register is the PASI TX Channel 1 configuration register.

Figure 7-26 PASI_TX_CH1_CFG Register

7	6	5	4	3	2	1	0
RESERVED		PASI_TX_CH1_CFG	PASI_TX_CH1_SLOT_NUM[4:0]
R-00b		R/W-1b	R/W-00000b

Table 7-27 PASI_TX_CH1_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R	0x0	Reserved bits; Write only reset values
5	PASI_TX_CH1_CFG	R/W	0x1	Primary ASI output channel 1 configuration. 0d = Primary ASI channel 1 output is in a tri-state condition 1d = Primary ASI channel 1 output corresponds to ADC/PDM Channel 1 data
4-0	PASI_TX_CH1_SLOT_NUM[4:0]	R/W	0x0	Primary ASI output channel 1 slot assignment. 0d = TDM is slot 0 or I²S, LJ is left slot 0 1d = TDM is slot 1 or I²S, LJ is left slot 1 2d to 14d = Slot assigned as per configuration 15d = TDM is slot 15 or I²S, LJ is left slot 15 16d = TDM is slot 16 or I²S, LJ is right slot 0 17d = TDM is slot 17 or I²S, LJ is right slot 1 18d to 30d = Slot assigned as per configuration 31d = TDM is slot 31 or I²S, LJ is right slot 15

7.1.27 PASI_TX_CH2_CFG Register (Address = 0x1F) [Reset = 0x21]

PASI_TX_CH2_CFG is shown in Figure 7-27 and described in Table 7-28.

Return to the Summary Table.

This register is the PASI TX Channel 2 configuration register.

Figure 7-27 PASI_TX_CH2_CFG Register

7	6	5	4	3	2	1	0
RESERVED		PASI_TX_CH2_CFG	PASI_TX_CH2_SLOT_NUM[4:0]
R-00b		R/W-1b	R/W-00001b

Table 7-28 PASI_TX_CH2_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R	0x0	Reserved bits; Write only reset values
5	PASI_TX_CH2_CFG	R/W	0x1	Primary ASI output channel 2 configuration. 0d = Primary ASI channel 2 output is in a tri-state condition 1d = Primary ASI channel 2 output corresponds to ADC/PDM Channel 2 data
4-0	PASI_TX_CH2_SLOT_NUM[4:0]	R/W	0x1	Primary ASI output channel 2 slot assignment. 0d = TDM is slot 0 or I²S, LJ is left slot 0 1d = TDM is slot 1 or I²S, LJ is left slot 1 2d to 14d = Slot assigned as per configuration 15d = TDM is slot 15 or I²S, LJ is left slot 15 16d = TDM is slot 16 or I²S, LJ is right slot 0 17d = TDM is slot 17 or I²S, LJ is right slot 1 18d to 30d = Slot assigned as per configuration 31d = TDM is slot 31 or I²S, LJ is right slot 15

7.1.28 PASI_TX_CH3_CFG Register (Address = 0x20) [Reset = 0x02]

PASI_TX_CH3_CFG is shown in Figure 7-28 and described in Table 7-29.

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This register is the PASI TX Channel 3 configuration register.

Figure 7-28 PASI_TX_CH3_CFG Register

7	6	5	4	3	2	1	0
RESERVED	PASI_TX_CH3_CFG[1:0]		PASI_TX_CH3_SLOT_NUM[4:0]
R-0b	R/W-00b		R/W-00010b

Table 7-29 PASI_TX_CH3_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0x0	Reserved bit; Write only reset value
6-5	PASI_TX_CH3_CFG[1:0]	R/W	0x0	Primary ASI output channel 3 configuration. 0d = Primary ASI channel 3 output is in a tri-state condition 1d = Primary ASI channel 3 output corresponds to PDM Channel 3 data 2d = Primary ASI channel 3 output corresponds to VBAT data 3d = Reserved
4-0	PASI_TX_CH3_SLOT_NUM[4:0]	R/W	0x2	Primary ASI output channel 3 slot assignment. 0d = TDM is slot 0 or I²S, LJ is left slot 0 1d = TDM is slot 1 or I²S, LJ is left slot 1 2d to 14d = Slot assigned as per configuration 15d = TDM is slot 15 or I²S, LJ is left slot 15 16d = TDM is slot 16 or I²S, LJ is right slot 0 17d = TDM is slot 17 or I²S, LJ is right slot 1 18d to 30d = Slot assigned as per configuration 31d = TDM is slot 31 or I²S, LJ is right slot 15

7.1.29 PASI_TX_CH4_CFG Register (Address = 0x21) [Reset = 0x03]

PASI_TX_CH4_CFG is shown in Figure 7-29 and described in Table 7-30.

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This register is the PASI TX Channel 4 configuration register.

Figure 7-29 PASI_TX_CH4_CFG Register

7	6	5	4	3	2	1	0
RESERVED	PASI_TX_CH4_CFG[1:0]		PASI_TX_CH4_SLOT_NUM[4:0]
R-0b	R/W-00b		R/W-00011b

Table 7-30 PASI_TX_CH4_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0x0	Reserved bit; Write only reset value
6-5	PASI_TX_CH4_CFG[1:0]	R/W	0x0	Primary ASI output channel 4 configuration. 0d = Primary ASI channel 4 output is in a tri-state condition 1d = Primary ASI channel 4 output corresponds to PDM Channel 4 data 2d = Primary ASI channel 4 output corresponds to TEMP data 3d = Reserved
4-0	PASI_TX_CH4_SLOT_NUM[4:0]	R/W	0x3	Primary ASI output channel 4 slot assignment. 0d = TDM is slot 0 or I²S, LJ is left slot 0 1d = TDM is slot 1 or I²S, LJ is left slot 1 2d to 14d = Slot assigned as per configuration 15d = TDM is slot 15 or I²S, LJ is left slot 15 16d = TDM is slot 16 or I²S, LJ is right slot 0 17d = TDM is slot 17 or I²S, LJ is right slot 1 18d to 30d = Slot assigned as per configuration 31d = TDM is slot 31 or I²S, LJ is right slot 15

7.1.30 PASI_TX_CH5_CFG Register (Address = 0x22) [Reset = 0x04]

PASI_TX_CH5_CFG is shown in Figure 7-30 and described in Table 7-31.

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This register is the PASI TX Channel 5 configuration register.

Figure 7-30 PASI_TX_CH5_CFG Register

7	6	5	4	3	2	1	0
RESERVED	PASI_TX_CH5_CFG[1:0]		PASI_TX_CH5_SLOT_NUM[4:0]
R-0b	R/W-00b		R/W-00100b

Table 7-31 PASI_TX_CH5_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0x0	Reserved bit; Write only reset value
6-5	PASI_TX_CH5_CFG[1:0]	R/W	0x0	Primary ASI output channel 5 configuration. 0d = Primary ASI channel 5 output is in a tri-state condition 1d = Primary ASI channel 5 output corresponds to ASI Input Channel 1 loopback data 2d = Primary ASI channel 5 output corresponds to echo reference Channel 1 data 3d = Reserved
4-0	PASI_TX_CH5_SLOT_NUM[4:0]	R/W	0x4	Primary ASI output channel 5 slot assignment. 0d = TDM is slot 0 or I²S, LJ is left slot 0 1d = TDM is slot 1 or I²S, LJ is left slot 1 2d to 14d = Slot assigned as per configuration 15d = TDM is slot 15 or I²S, LJ is left slot 15 16d = TDM is slot 16 or I²S, LJ is right slot 0 17d = TDM is slot 17 or I²S, LJ is right slot 1 18d to 30d = Slot assigned as per configuration 31d = TDM is slot 31 or I²S, LJ is right slot 15

7.1.31 PASI_TX_CH6_CFG Register (Address = 0x23) [Reset = 0x05]

PASI_TX_CH6_CFG is shown in Figure 7-31 and described in Table 7-32.

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This register is the PASI TX Channel 6 configuration register.

Figure 7-31 PASI_TX_CH6_CFG Register

7	6	5	4	3	2	1	0
RESERVED	PASI_TX_CH6_CFG[1:0]		PASI_TX_CH6_SLOT_NUM[4:0]
R-0b	R/W-00b		R/W-00101b

Table 7-32 PASI_TX_CH6_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0x0	Reserved bit; Write only reset value
6-5	PASI_TX_CH6_CFG[1:0]	R/W	0x0	Primary ASI output channel 6 configuration. 0d = Primary ASI channel 6 output is in a tri-state condition 1d = Primary ASI channel 6 output corresponds to ASI Input Channel 2 loopback data 2d = Primary ASI channel 6 output corresponds to echo reference Channel 2 data 3d = Reserved
4-0	PASI_TX_CH6_SLOT_NUM[4:0]	R/W	0x5	Primary ASI output channel 6 slot assignment. 0d = TDM is slot 0 or I²S, LJ is left slot 0 1d = TDM is slot 1 or I²S, LJ is left slot 1 2d to 14d = Slot assigned as per configuration 15d = TDM is slot 15 or I²S, LJ is left slot 15 16d = TDM is slot 16 or I²S, LJ is right slot 0 17d = TDM is slot 17 or I²S, LJ is right slot 1 18d to 30d = Slot assigned as per configuration 31d = TDM is slot 31 or I²S, LJ is right slot 15

7.1.32 PASI_TX_CH7_CFG Register (Address = 0x24) [Reset = 0x06]

PASI_TX_CH7_CFG is shown in Figure 7-32 and described in Table 7-33.

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This register is the PASI TX Channel 7 configuration register.

Figure 7-32 PASI_TX_CH7_CFG Register

7	6	5	4	3	2	1	0
RESERVED	PASI_TX_CH7_CFG[1:0]		PASI_TX_CH7_SLOT_NUM[4:0]
R-0b	R/W-00b		R/W-00110b

Table 7-33 PASI_TX_CH7_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0x0	Reserved bit; Write only reset value
6-5	PASI_TX_CH7_CFG[1:0]	R/W	0x0	Primary ASI output channel 7 configuration. 0d = Primary ASI channel 7 output is in a tri-state condition 1d = Primary ASI channel 7 output corresponds to {VBAT_WLby2, TEMP_WLby2} 2d = Primary ASI channel 7 output corresponds to {echo_ref_ch1, echo_ref_ch2} 3d = Reserved
4-0	PASI_TX_CH7_SLOT_NUM[4:0]	R/W	0x6	Primary ASI output channel 7 slot assignment. 0d = TDM is slot 0 or I²S, LJ is left slot 0 1d = TDM is slot 1 or I²S, LJ is left slot 1 2d to 14d = Slot assigned as per configuration 15d = TDM is slot 15 or I²S, LJ is left slot 15 16d = TDM is slot 16 or I²S, LJ is right slot 0 17d = TDM is slot 17 or I²S, LJ is right slot 1 18d to 30d = Slot assigned as per configuration 31d = TDM is slot 31 or I²S, LJ is right slot 15

7.1.33 PASI_TX_CH8_CFG Register (Address = 0x25) [Reset = 0x07]

PASI_TX_CH8_CFG is shown in Figure 7-33 and described in Table 7-34.

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This register is the PASI TX Channel 8 configuration register.

Figure 7-33 PASI_TX_CH8_CFG Register

7	6	5	4	3	2	1	0
RESERVED		PASI_TX_CH8_CFG	PASI_TX_CH8_SLOT_NUM[4:0]
R-00b		R/W-0b	R/W-00111b

Table 7-34 PASI_TX_CH8_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R	0x0	Reserved bits; Write only reset values
5	PASI_TX_CH8_CFG	R/W	0x0	Primary ASI output channel 8 configuration. 0d = Primary ASI channel 8 output is in a tri-state condition 1d = Primary ASI channel 8 output corresponds to ICLA data
4-0	PASI_TX_CH8_SLOT_NUM[4:0]	R/W	0x7	Primary ASI output channel 8 slot assignment. 0d = TDM is slot 0 or I²S, LJ is left slot 0 1d = TDM is slot 1 or I²S, LJ is left slot 1 2d to 14d = Slot assigned as per configuration 15d = TDM is slot 15 or I²S, LJ is left slot 15 16d = TDM is slot 16 or I²S, LJ is right slot 0 17d = TDM is slot 17 or I²S, LJ is right slot 1 18d to 30d = Slot assigned as per configuration 31d = TDM is slot 31 or I²S, LJ is right slot 15

7.1.34 PASI_RX_CFG0 Register (Address = 0x26) [Reset = 0x00]

PASI_RX_CFG0 is shown in Figure 7-34 and described in Table 7-35.

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This register is the PASI RX configuration register 0.

Figure 7-34 PASI_RX_CFG0 Register

7	6	5	4	3	2	1	0
PASI_RX_EDGE	PASI_RX_USE_INT_FSYNC	PASI_RX_USE_INT_BCLK	PASI_RX_OFFSET[4:0]
R/W-0b	R/W-0b	R/W-0b	R/W-00000b

Table 7-35 PASI_RX_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	PASI_RX_EDGE	R/W	0x0	Primary ASI data input (on the primary and secondary data pin) receive edge. 0d = Default edge as per the protocol configuration setting in PASI_BCLK_POL 1d = Inverted following edge (half cycle delay) with respect to the default edge setting
6	PASI_RX_USE_INT_FSYNC	R/W	0x0	Primary ASI uses internal FSYNC for input data latching in Controller mode configuration as applicable. 0d = Use external FSYNC for ASI protocol data latching 1d = Use internal FSYNC for ASI protocol data latching
5	PASI_RX_USE_INT_BCLK	R/W	0x0	Primary ASI uses internal BCLK for input data latching in Controller mode configuration. 0d = Use external BCLK for ASI protocol data latching 1d = Use internal BCLK for ASI protocol data latching
4-0	PASI_RX_OFFSET[4:0]	R/W	0x0	Primary ASI data input MSB slot 0 offset (on the primary and secondary data pin). 0d = ASI data MSB location has no offset and is as per standard protocol 1d = ASI data MSB location (TDM mode is slot 0 or I²S, LJ mode is the left and right slot 0) offset of one BCLK cycle with respect to standard protocol 2d = ASI data MSB location (TDM mode is slot 0 or I²S, LJ mode is the left and right slot 0) offset of two BCLK cycles with respect to standard protocol 3d to 30d = ASI data MSB location (TDM mode is slot 0 or I²S, LJ mode is the left and right slot 0) offset assigned as per configuration 31d = ASI data MSB location (TDM mode is slot 0 or I²S, LJ mode is the left and right slot 0) offset of 31 BCLK cycles with respect to standard protocol

7.1.35 PASI_RX_CFG1 Register (Address = 0x27) [Reset = 0x00]

PASI_RX_CFG1 is shown in Figure 7-35 and described in Table 7-36.

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This register is the PASI RX configuration register 1.

Figure 7-35 PASI_RX_CFG1 Register

7	6	5	4	3	2	1	0
PASI_RX_CH8_SEL	PASI_RX_CH7_SEL	PASI_RX_CH6_SEL	PASI_RX_CH5_SEL	PASI_RX_CH4_SEL	PASI_RX_CH3_SEL	PASI_RX_CH2_SEL	PASI_RX_CH1_SEL
R/W-0b	R/W-0b	R/W-0b	R/W-0b	R/W-0b	R/W-0b	R/W-0b	R/W-0b

Table 7-36 PASI_RX_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	PASI_RX_CH8_SEL	R/W	0x0	Primary ASI input channel 8 select. 0d = Primary ASI channel 8 input is on DIN 1d = Primary ASI channel 8 input is on DIN2
6	PASI_RX_CH7_SEL	R/W	0x0	Primary ASI input channel 7 select. 0d = Primary ASI channel 7 input is on DIN 1d = Primary ASI channel 7 input is on DIN2
5	PASI_RX_CH6_SEL	R/W	0x0	Primary ASI input channel 6 select. 0d = Primary ASI channel 6 input is on DIN 1d = Primary ASI channel 6 input is on DIN2
4	PASI_RX_CH5_SEL	R/W	0x0	Primary ASI input channel 5 select. 0d = Primary ASI channel 5 input is on DIN 1d = Primary ASI channel 5 input is on DIN2
3	PASI_RX_CH4_SEL	R/W	0x0	Primary ASI input channel 4 select. 0d = Primary ASI channel 4 input is on DIN 1d = Primary ASI channel 4 input is on DIN2
2	PASI_RX_CH3_SEL	R/W	0x0	Primary ASI input channel 3 select. 0d = Primary ASI channel 3 input is on DIN 1d = Primary ASI channel 3 input is on DIN2
1	PASI_RX_CH2_SEL	R/W	0x0	Primary ASI input channel 2 select. 0d = Primary ASI channel 2 input is on DIN 1d = Primary ASI channel 2 input is on DIN2
0	PASI_RX_CH1_SEL	R/W	0x0	Primary ASI input channel 1 select. 0d = Primary ASI channel 1 input is on DIN 1d = Primary ASI channel 1 input is on DIN2

7.1.36 PASI_RX_CH1_CFG Register (Address = 0x28) [Reset = 0x20]

PASI_RX_CH1_CFG is shown in Figure 7-36 and described in Table 7-37.

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This register is the PASI RX Channel 1 configuration register.

Figure 7-36 PASI_RX_CH1_CFG Register

7	6	5	4	3	2	1	0
RESERVED		PASI_RX_CH1_CFG	PASI_RX_CH1_SLOT_NUM[4:0]
R-00b		R/W-1b	R/W-00000b

Table 7-37 PASI_RX_CH1_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R	0x0	Reserved bits; Write only reset values
5	PASI_RX_CH1_CFG	R/W	0x1	Primary ASI input channel 1 configuration. 0d = Primary ASI channel 1 input is disabled 1d = Primary ASI channel 1 input corresponds to DAC Channel 1 data
4-0	PASI_RX_CH1_SLOT_NUM[4:0]	R/W	0x0	Primary ASI input channel 1 slot assignment. 0d = TDM is slot 0 or I²S, LJ is left slot 0 1d = TDM is slot 1 or I²S, LJ is left slot 1 2d to 14d = Slot assigned as per configuration 15d = TDM is slot 15 or I²S, LJ is left slot 15 16d = TDM is slot 16 or I²S, LJ is right slot 0 17d = TDM is slot 17 or I²S, LJ is right slot 1 18d to 30d = Slot assigned as per configuration 31d = TDM is slot 31 or I²S, LJ is right slot 15

7.1.37 PASI_RX_CH2_CFG Register (Address = 0x29) [Reset = 0x21]

PASI_RX_CH2_CFG is shown in Figure 7-37 and described in Table 7-38.

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This register is the PASI RX Channel 2 configuration register.

Figure 7-37 PASI_RX_CH2_CFG Register

7	6	5	4	3	2	1	0
RESERVED		PASI_RX_CH2_CFG	PASI_RX_CH2_SLOT_NUM[4:0]
R-00b		R/W-1b	R/W-00001b

Table 7-38 PASI_RX_CH2_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R	0x0	Reserved bits; Write only reset values
5	PASI_RX_CH2_CFG	R/W	0x1	Primary ASI input channel 2 configuration. 0d = Primary ASI channel 2 input is disabled 1d = Primary ASI channel 2 input corresponds to DAC Channel 2 data
4-0	PASI_RX_CH2_SLOT_NUM[4:0]	R/W	0x1	Primary ASI input channel 2 slot assignment. 0d = TDM is slot 0 or I²S, LJ is left slot 0 1d = TDM is slot 1 or I²S, LJ is left slot 1 2d to 14d = Slot assigned as per configuration 15d = TDM is slot 15 or I²S, LJ is left slot 15 16d = TDM is slot 16 or I²S, LJ is right slot 0 17d = TDM is slot 17 or I²S, LJ is right slot 1 18d to 30d = Slot assigned as per configuration 31d = TDM is slot 31 or I²S, LJ is right slot 15

7.1.38 PASI_RX_CH3_CFG Register (Address = 0x2A) [Reset = 0x02]

PASI_RX_CH3_CFG is shown in Figure 7-38 and described in Table 7-39.

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This register is the PASI RX Channel 3 configuration register.

Figure 7-38 PASI_RX_CH3_CFG Register

7	6	5	4	3	2	1	0
RESERVED		PASI_RX_CH3_CFG	PASI_RX_CH3_SLOT_NUM[4:0]
R-00b		R/W-0b	R/W-00010b

Table 7-39 PASI_RX_CH3_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R	0x0	Reserved bits; Write only reset values
5	PASI_RX_CH3_CFG	R/W	0x0	Primary ASI input channel 3 configuration. 0d = Primary ASI channel 3 input is disabled 1d = Primary ASI channel 3 input corresponds to DAC Channel 3 data
4-0	PASI_RX_CH3_SLOT_NUM[4:0]	R/W	0x2	Primary ASI input channel 3 slot assignment. 0d = TDM is slot 0 or I²S, LJ is left slot 0 1d = TDM is slot 1 or I²S, LJ is left slot 1 2d to 14d = Slot assigned as per configuration 15d = TDM is slot 15 or I²S, LJ is left slot 15 16d = TDM is slot 16 or I²S, LJ is right slot 0 17d = TDM is slot 17 or I²S, LJ is right slot 1 18d to 30d = Slot assigned as per configuration 31d = TDM is slot 31 or I²S, LJ is right slot 15

7.1.39 PASI_RX_CH4_CFG Register (Address = 0x2B) [Reset = 0x03]

PASI_RX_CH4_CFG is shown in Figure 7-39 and described in Table 7-40.

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This register is the PASI RX Channel 4 configuration register.

Figure 7-39 PASI_RX_CH4_CFG Register

7	6	5	4	3	2	1	0
RESERVED		PASI_RX_CH4_CFG	PASI_RX_CH4_SLOT_NUM[4:0]
R-00b		R/W-0b	R/W-00011b

Table 7-40 PASI_RX_CH4_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R	0x0	Reserved bits; Write only reset values
5	PASI_RX_CH4_CFG	R/W	0x0	Primary ASI input channel 4 configuration. 0d = Primary ASI channel 4 input is disabled 1d = Primary ASI channel 4 input corresponds to DAC Channel 4 data
4-0	PASI_RX_CH4_SLOT_NUM[4:0]	R/W	0x3	Primary ASI input channel 4 slot assignment. 0d = TDM is slot 0 or I²S, LJ is left slot 0 1d = TDM is slot 1 or I²S, LJ is left slot 1 2d to 14d = Slot assigned as per configuration 15d = TDM is slot 15 or I²S, LJ is left slot 15 16d = TDM is slot 16 or I²S, LJ is right slot 0 17d = TDM is slot 17 or I²S, LJ is right slot 1 18d to 30d = Slot assigned as per configuration 31d = TDM is slot 31 or I²S, LJ is right slot 15

7.1.40 PASI_RX_CH5_CFG Register (Address = 0x2C) [Reset = 0x04]

PASI_RX_CH5_CFG is shown in Figure 7-40 and described in Table 7-41.

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This register is the PASI RX Channel 5 configuration register.

Figure 7-40 PASI_RX_CH5_CFG Register

7	6	5	4	3	2	1	0
RESERVED	PASI_RX_CH5_CFG[1:0]		PASI_RX_CH5_SLOT_NUM[4:0]
R-0b	R/W-00b		R/W-00100b

Table 7-41 PASI_RX_CH5_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0x0	Reserved bit; Write only reset value
6-5	PASI_RX_CH5_CFG[1:0]	R/W	0x0	Primary ASI input channel 5 configuration. 0d = Primary ASI channel 5 input is disabled 1d = Primary ASI channel 5 input corresponds to DAC Channel 5 data 2d = Primary ASI channel 5 input corresponds to ADC Channel 1 output loopback 3d = Reserved
4-0	PASI_RX_CH5_SLOT_NUM[4:0]	R/W	0x4	Primary ASI input channel 5 slot assignment. 0d = TDM is slot 0 or I²S, LJ is left slot 0 1d = TDM is slot 1 or I²S, LJ is left slot 1 2d to 14d = Slot assigned as per configuration 15d = TDM is slot 15 or I²S, LJ is left slot 15 16d = TDM is slot 16 or I²S, LJ is right slot 0 17d = TDM is slot 17 or I²S, LJ is right slot 1 18d to 30d = Slot assigned as per configuration 31d = TDM is slot 31 or I²S, LJ is right slot 15

7.1.41 PASI_RX_CH6_CFG Register (Address = 0x2D) [Reset = 0x05]

PASI_RX_CH6_CFG is shown in Figure 7-41 and described in Table 7-42.

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This register is the PASI RX Channel 6 configuration register.

Figure 7-41 PASI_RX_CH6_CFG Register

7	6	5	4	3	2	1	0
RESERVED	PASI_RX_CH6_CFG[1:0]		PASI_RX_CH6_SLOT_NUM[4:0]
R-0b	R/W-00b		R/W-00101b

Table 7-42 PASI_RX_CH6_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0x0	Reserved bit; Write only reset value
6-5	PASI_RX_CH6_CFG[1:0]	R/W	0x0	Primary ASI input channel 6 configuration. 0d = Primary ASI channel 6 input is disabled 1d = Primary ASI channel 6 input corresponds to DAC Channel 6 data 2d = Primary ASI channel 6 input corresponds to ADC Channel 2 output loopback 3d = Primary ASI channel 6 input corresponds to ICLA device 1 data
4-0	PASI_RX_CH6_SLOT_NUM[4:0]	R/W	0x5	Primary ASI input channel 6 slot assignment. 0d = TDM is slot 0 or I²S, LJ is left slot 0 1d = TDM is slot 1 or I²S, LJ is left slot 1 2d to 14d = Slot assigned as per configuration 15d = TDM is slot 15 or I²S, LJ is left slot 15 16d = TDM is slot 16 or I²S, LJ is right slot 0 17d = TDM is slot 17 or I²S, LJ is right slot 1 18d to 30d = Slot assigned as per configuration 31d = TDM is slot 31 or I²S, LJ is right slot 15

7.1.42 PASI_RX_CH7_CFG Register (Address = 0x2E) [Reset = 0x06]

PASI_RX_CH7_CFG is shown in Figure 7-42 and described in Table 7-43.

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This register is the PASI RX Channel 7 configuration register.

Figure 7-42 PASI_RX_CH7_CFG Register

7	6	5	4	3	2	1	0
RESERVED	PASI_RX_CH7_CFG[1:0]		PASI_RX_CH7_SLOT_NUM[4:0]
R-0b	R/W-00b		R/W-00110b

Table 7-43 PASI_RX_CH7_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0x0	Reserved bit; Write only reset value
6-5	PASI_RX_CH7_CFG[1:0]	R/W	0x0	Primary ASI input channel 7 configuration. 0d = Primary ASI channel 7 input is disabled 1d = Primary ASI channel 7 input corresponds to DAC Channel 7 data 2d = Primary ASI channel 7 input corresponds to ADC Channel 3 output loopback 3d = Primary ASI channel 7 input corresponds to ICLA device 2 data
4-0	PASI_RX_CH7_SLOT_NUM[4:0]	R/W	0x6	Primary ASI input channel 7 slot assignment. 0d = TDM is slot 0 or I²S, LJ is left slot 0 1d = TDM is slot 1 or I²S, LJ is left slot 1 2d to 14d = Slot assigned as per configuration 15d = TDM is slot 15 or I²S, LJ is left slot 15 16d = TDM is slot 16 or I²S, LJ is right slot 0 17d = TDM is slot 17 or I²S, LJ is right slot 1 18d to 30d = Slot assigned as per configuration 31d = TDM is slot 31 or I²S, LJ is right slot 15

7.1.43 PASI_RX_CH8_CFG Register (Address = 0x2F) [Reset = 0x07]

PASI_RX_CH8_CFG is shown in Figure 7-43 and described in Table 7-44.

Return to the Summary Table.

This register is the PASI RX Channel 8 configuration register.

Figure 7-43 PASI_RX_CH8_CFG Register

7	6	5	4	3	2	1	0
RESERVED	PASI_RX_CH8_CFG[1:0]		PASI_RX_CH8_SLOT_NUM[4:0]
R-0b	R/W-00b		R/W-00111b

Table 7-44 PASI_RX_CH8_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0x0	Reserved bit; Write only reset value
6-5	PASI_RX_CH8_CFG[1:0]	R/W	0x0	Primary ASI input channel 8 configuration. 0d = Primary ASI channel 8 input is disabled 1d = Primary ASI channel 8 input corresponds to DAC Channel 8 data 2d = Primary ASI channel 8 input corresponds to ADC Channel 4 output loopback 3d = Primary ASI channel 8 input corresponds to ICLA device 3 data
4-0	PASI_RX_CH8_SLOT_NUM[4:0]	R/W	0x7	Primary ASI input channel 8 slot assignment. 0d = TDM is slot 0 or I²S, LJ is left slot 0 1d = TDM is slot 1 or I²S, LJ is left slot 1 2d to 14d = Slot assigned as per configuration 15d = TDM is slot 15 or I²S, LJ is left slot 15 16d = TDM is slot 16 or I²S, LJ is right slot 0 17d = TDM is slot 17 or I²S, LJ is right slot 1 18d to 30d = Slot assigned as per configuration 31d = TDM is slot 31 or I²S, LJ is right slot 15

7.1.44 CLK_CFG0 Register (Address = 0x32) [Reset = 0x00]

CLK_CFG0 is shown in Figure 7-44 and described in Table 7-45.

Return to the Summary Table.

This register is the clock configuration register 0.

Figure 7-44 CLK_CFG0 Register

7	6	5	4	3	2	1	0
PASI_SAMP_RATE[5:0]						PASI_FS_RATE_NO_LIM	CUSTOM_CLK_CFG
R/W-000000b						R/W-0b	R/W-0b

Table 7-45 CLK_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-2	PASI_SAMP_RATE[5:0]	R/W	0x0	Primary ASI sample rate configuration. -Typical (Allowed Range) 0d = Primary ASI sampling rate auto detected in the device 1d = 768000 (670320-791040) 2d = 614400 (536256-632832) 3d = 512000 (446880-527360) 4d = 438857 (383040-452022) 5d = 384000 (335160-395520) 6d = 341333 (297920-351573) 7d = 307200 (268128-316416) 8d = 256000 (223440-263680) 9d = 219429 (191520-226011) 10d = 192000 (167580-197760) 11d = 170667 (148960-175786) 12d = 153600 (134064-158208) 13d = 128000 (111720-131840) 14d = 109714 (95760-113005) 15d = 96000 (83790-98880) 16d = 85333 (74480-87893) 17d = 76800 (67032-79104) 18d = 64000 (55860-65920) 19d = 54857 (47880-56502) 20d = 48000 (41895-49440) 21d = 42667 (37240-43946) 22d = 38400 (33516-39552) 23d = 32000 (27930-32960) 24d = 27429 (23940-28251) 25d = 24000 (20947-24720) 26d = 21333 (18620-21973) 27d = 19200 (16758-19776) 28d = 16000 (13965-16480) 29d = 13714 (11970-14125) 30d = 12000 (10473-12360) 31d = 10667 (9310-10986) 32d = 9600 (8379-9888) 33d = 8000 (6982-8240) 34d = 6857 (5985-7062) 35d = 6000 (5236-6180) 36d = 5333 (4655-5493) 37d = 4800 (4189-4944) 38d = 4000 (3491-4120) 39d = 3429 (2992-3531) 40d = 3000 (2618-3090) 41d-63d = Reserved
1	PASI_FS_RATE_NO_LIM	R/W	0x0	Limit sampling rate to standard audio sample rates only. 0d = Standard audio rates with 1% tolerance supported using auto mode 1d = Standard audio rates with 5% tolerance supported using auto mode
0	CUSTOM_CLK_CFG	R/W	0x0	Custom clock configuration enable, all dividers and mux selects need to be manually configured. 0d = Auto clock configuration 1d = Custom clock configuration

7.1.45 CLK_CFG1 Register (Address = 0x33) [Reset = 0x00]

CLK_CFG1 is shown in Figure 7-45 and described in Table 7-46.

Return to the Summary Table.

This register is the clock configuration register 1.

Figure 7-45 CLK_CFG1 Register

7	6	5	4	3	2	1	0
SASI_SAMP_RATE[5:0]						SASI_FS_RATE_NO_LIM	RESERVED
R/W-000000b						R/W-0b	R-0b

Table 7-46 CLK_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-2	SASI_SAMP_RATE[5:0]	R/W	0x0	Secondary ASI sample rate configuration. -Typical (Range) 0d = Secondary ASI sampling rate auto detected in the device 1d = 768000 (670320-791040) 2d = 614400 (536256-632832) 3d = 512000 (446880-527360) 4d = 438857 (383040-452022) 5d = 384000 (335160-395520) 6d = 341333 (297920-351573) 7d = 307200 (268128-316416) 8d = 256000 (223440-263680) 9d = 219429 (191520-226011) 10d = 192000 (167580-197760) 11d = 170667 (148960-175786) 12d = 153600 (134064-158208) 13d = 128000 (111720-131840) 14d = 109714 (95760-113005) 15d = 96000 (83790-98880) 16d = 85333 (74480-87893) 17d = 76800 (67032-79104) 18d = 64000 (55860-65920) 19d = 54857 (47880-56502) 20d = 48000 (41895-49440) 21d = 42667 (37240-43946) 22d = 38400 (33516-39552) 23d = 32000 (27930-32960) 24d = 27429 (23940-28251) 25d = 24000 (20947-24720) 26d = 21333 (18620-21973) 27d = 19200 (16758-19776) 28d = 16000 (13965-16480) 29d = 13714 (11970-14125) 30d = 12000 (10473-12360) 31d = 10667 (9310-10986) 32d = 9600 (8379-9888) 33d = 8000 (6982-8240) 34d = 6857 (5985-7062) 35d = 6000 (5236-6180) 36d = 5333 (4655-5493) 37d = 4800 (4189-4944) 38d = 4000 (3491-4120) 39d = 3429 (2992-3531) 40d = 3000 (2618-3090) 41d-63d = Reserved
1	SASI_FS_RATE_NO_LIM	R/W	0x0	Limit sampling rate to standard audio sample rates only. 0d = Standard audio rates with 1% tolerance supported using auto mode 1d = Standard audio rates with 5% tolerance supported using auto mode
0	RESERVED	R	0x0	Reserved bit; Write only reset value

7.1.46 CLK_CFG2 Register (Address = 0x34) [Reset = 0x40]

CLK_CFG2 is shown in Figure 7-46 and described in Table 7-47.

Return to the Summary Table.

This register is the clock configuration register 2.

Figure 7-46 CLK_CFG2 Register

7	6	5	4	3	2	1	0
PLL_DIS	AUTO_PLL_FR_ALLOW	RESERVED	RESERVED	CLK_SRC_SEL[2:0]			RATIO_CLK_EDGE
R/W-0b	R/W-1b	R-0b	R-0b	R/W-000b			R/W-0b

Table 7-47 CLK_CFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	PLL_DIS	R/W	0x0	Custom/Auto clock mode PLL setting. 0d = PLL is always enabled in custom clk mode/PLL is enabled based on DSP MIPS requirement in auto clock mode 1d = PLL is disabled
6	AUTO_PLL_FR_ALLOW	R/W	0x1	Allow the PLL to operate in fractional mode of operation. 0d = PLL fractional mode disabled 1d = PLL fractional mode allowed
5	RESERVED	R	0x0	Reserved bit; Write only reset value
4	RESERVED	R	0x0	Reserved bit; Write only reset value
3-1	CLK_SRC_SEL[2:0]	R/W	0x0	Input clock source select. 0d = Primary ASI BCLK is the input clock source 1d = cclk synchronized with Primary ASI FSYNC is the input clock source 2d = Secondary ASI BCLK is the input clock source 3d = cclk synchronized with Secondary ASI FSYNC is the input clock source 4d = Fixed cclk frequency (used only in controller mode configuration) 5d = Internal oscillator clock is the input clock source 6d to 7d = Reserved
0	RATIO_CLK_EDGE	R/W	0x0	Edge selection for clock source ratio detection. 0d = Use rising edge of clock source to check ratio with primary or secondary FSYNC 1d = Use falling edge of clock source to check ratio with primary or secondary FSYNC

7.1.47 CNT_CLK_CFG0 Register (Address = 0x35) [Reset = 0x00]

CNT_CLK_CFG0 is shown in Figure 7-47 and described in Table 7-48.

Return to the Summary Table.

This register is the controller mode clock configuration register 0.

Figure 7-47 CNT_CLK_CFG0 Register

7	6	5	4	3	2	1	0
PDM_CLK_CFG[1:0]		CCLK_FS_RATIO_MSB[5:0]
R/W-00b		R/W-000000b

Table 7-48 CNT_CLK_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	PDM_CLK_CFG[1:0]	R/W	0x0	PDM_CLK configurattion. 0d = PDM_CLK is 2.8224 MHz or 3.072 MHz 1d = PDM_CLK is 1.4112 MHz or 1.536 MHz 2d = PDM_CLK is 705.6 kHz or 768 kHz 3d = PDM_CLK is 5.6448 MHz or 6.144 MHz
5-0	CCLK_FS_RATIO_MSB[5:0]	R/W	0x0	Most significant bits for selecting the ratio between cclk and primary/secondary ASI FSYNC with which cclk is synchonized. 0d = Auto detect the ratio (assumption is cclk is synchronized with primary/secondary FSYNC) 1d to 16383d = Ratio as per configuration

7.1.48 CNT_CLK_CFG1 Register (Address = 0x36) [Reset = 0x00]

CNT_CLK_CFG1 is shown in Figure 7-48 and described in Table 7-49.

Return to the Summary Table.

This register is the controller mode clock configuration register 1.

Figure 7-48 CNT_CLK_CFG1 Register

7	6	5	4	3	2	1	0
CCLK_FS_RATIO_LSB[7:0]
R/W-00000000b

Table 7-49 CNT_CLK_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	CCLK_FS_RATIO_LSB[7:0]	R/W	0x0	Select the ratio between cclk and primary/secondary ASI FSYNC with which cclk is synchonized. 0d = Auto detect the ratio (assumption is cclk is synchronized with primary/secondary FSYNC) 1d to 16383d = Ratio as per configuration

7.1.49 CNT_CLK_CFG2 Register (Address = 0x37) [Reset = 0x20]

CNT_CLK_CFG2 is shown in Figure 7-49 and described in Table 7-50.

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This register is the controller mode clock configuration register 2.

Figure 7-49 CNT_CLK_CFG2 Register

7	6	5	4	3	2	1	0
CCLK_FREQ_SEL[2:0]			PASI_CNT_CFG	SASI_CNT_CFG	RESERVED	RESERVED	FS_MODE
R/W-001b			R/W-0b	R/W-0b	R-0b	R-0b	R/W-0b

Table 7-50 CNT_CLK_CFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-5	CCLK_FREQ_SEL[2:0]	R/W	0x1	These bits select the CCLK input frequency (used only in controller mode configuration). 0d = 12 MHz 1d = 12.288 MHz 2d = 13 MHz 3d = 16 MHz 4d = 19.2 MHz 5d = 19.68 MHz 6d = 24 MHz 7d = 24.576 MHz
4	PASI_CNT_CFG	R/W	0x0	Primary ASI controller or target configuration 0d = Primary ASI in target configuration 1d = Primary ASI in controller configuration
3	SASI_CNT_CFG	R/W	0x0	Secondary ASI controller or target configuration 0d = Secondary ASI in target configuration 1d = Secondary ASI in controller configuration
2	RESERVED	R	0x0	Reserved bit; Write only reset value
1	RESERVED	R	0x0	Reserved bit; Write only reset value
0	FS_MODE	R/W	0x0	Sample rate setting (valid when the device is in controller mode). This is applicable for both PASI and SASI. 0d = sampling rate is a multiple (or submultiple) of 48 kHz 1d = sampling rate is a multiple (or submultiple) of 44.1 kHz

7.1.50 CNT_CLK_CFG3 Register (Address = 0x38) [Reset = 0x00]

CNT_CLK_CFG3 is shown in Figure 7-50 and described in Table 7-51.

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This register is the controller mode clock configuration register 3.

Figure 7-50 CNT_CLK_CFG3 Register

7	6	5	4	3	2	1	0
PASI_USE_INT_BCLK_FOR_FSYNC	PASI_INV_BCLK_FOR_FSYNC	PASI_BCLK_FS_RATIO_MSB[5:0]
R/W-0b	R/W-0b	R/W-000000b

Table 7-51 CNT_CLK_CFG3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	PASI_USE_INT_BCLK_FOR_FSYNC	R/W	0x0	Use internal BCLK for FSYNC generation in PASI during controller mode configuration. 0d = Use external BCLK for FSYNC generation 1d = Use internal BCLK for FSYNC generation
6	PASI_INV_BCLK_FOR_FSYNC	R/W	0x0	Invert PASI BCLK polarity only for PASI FSYNC generation in controller mode configuration. 0d = Do not invert PASI BCLK polarity for PASI FSYNC generation 1d = Invert PASI BCLK polarity for PASI FSYNC generation
5-0	PASI_BCLK_FS_RATIO_MSB[5:0]	R/W	0x0	MSB bits for primary ASI BCLK to FSYNC ratio in controller mode.

7.1.51 CNT_CLK_CFG4 Register (Address = 0x39) [Reset = 0x00]

CNT_CLK_CFG4 is shown in Figure 7-51 and described in Table 7-52.

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This register is the controller mode clock configuration register 4.

Figure 7-51 CNT_CLK_CFG4 Register

7	6	5	4	3	2	1	0
PASI_BCLK_FS_RATIO_LSB[7:0]
R/W-00000000b

Table 7-52 CNT_CLK_CFG4 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	PASI_BCLK_FS_RATIO_LSB[7:0]	R/W	0x0	LSB byte for primary ASI BCLK to FSYNC ratio in controller mode.

7.1.52 CNT_CLK_CFG5 Register (Address = 0x3A) [Reset = 0x00]

CNT_CLK_CFG5 is shown in Figure 7-52 and described in Table 7-53.

Return to the Summary Table.

This register is the controller mode clock configuration register 5.

Figure 7-52 CNT_CLK_CFG5 Register

7	6	5	4	3	2	1	0
SASI_USE_INT_BCLK_FOR_FSYNC	SASI_INV_BCLK_FOR_FSYNC	SASI_BCLK_FS_RATIO_MSB[5:0]
R/W-0b	R/W-0b	R/W-000000b

Table 7-53 CNT_CLK_CFG5 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	SASI_USE_INT_BCLK_FOR_FSYNC	R/W	0x0	Use internal BCLK for FSYNC generation in SASI during controller mode configuration. 0d = Use external BCLK for FSYNC generation 1d = Use internal BCLK for FSYNC generation
6	SASI_INV_BCLK_FOR_FSYNC	R/W	0x0	Invert SASI BCLK polarity only for SASI FSYNC generation in controller mode configuration. 0d = Do not invert SASI BCLK polarity for SASI FSYNC generation 1d = Invert SASI BCLK polarity for SASI FSYNC generation
5-0	SASI_BCLK_FS_RATIO_MSB[5:0]	R/W	0x0	MSB bits for secondary ASI BCLK to FSYNC ratio in controller mode.

7.1.53 CNT_CLK_CFG6 Register (Address = 0x3B) [Reset = 0x00]

CNT_CLK_CFG6 is shown in Figure 7-53 and described in Table 7-54.

Return to the Summary Table.

This register is the controller mode clock configuration register 6.

Figure 7-53 CNT_CLK_CFG6 Register

7	6	5	4	3	2	1	0
SASI_BCLK_FS_RATIO_LSB[7:0]
R/W-00000000b

Table 7-54 CNT_CLK_CFG6 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	SASI_BCLK_FS_RATIO_LSB[7:0]	R/W	0x0	LSB byte for secondary ASI BCLK to FSYNC ratio in controller mode.

7.1.54 CLK_ERR_STS0 Register (Address = 0x3C) [Reset = 0x00]

CLK_ERR_STS0 is shown in Figure 7-54 and described in Table 7-55.

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This register is the clock error and status register 0.

Figure 7-54 CLK_ERR_STS0 Register

7	6	5	4	3	2	1	0
DSP_CLK_ERR	RESERVED	RESERVED	SRC_RATIO_ERR	DEM_RATE_ERR	PDM_CLK_ERR	RESET_ON_CLK_STOP_DET_STS	RESERVED
R-0b	R-0b	R-0b	R-0b	R-0b	R-0b	R-0b	R-0b

Table 7-55 CLK_ERR_STS0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	DSP_CLK_ERR	R	0x0	Flag indicating ratio error between FSYNC and selected clock source. 0d = No ratio error 1d = Ratio error between primary or secondary ASI FSYNC and selected clock source
6	RESERVED	R	0x0	Reserved bit; Write only reset value
5	RESERVED	R	0x0	Reserved bit; Write only reset value
4	SRC_RATIO_ERR	R	0x0	Flag indicating that SRC m:n ratio is unsupported. (not valid for custom m/n ratio config). 0d = m:n ratio supported 1d = Unsupported m:n ratio error
3	DEM_RATE_ERR	R	0x0	Flag indicating that clock configuration does not allow valid DEM rate. 0d = No DEM clock rate error 1d = DEM clock rate error in selected clock configuration
2	PDM_CLK_ERR	R	0x0	Flag indicating that clock configuration does not allow valid PDM clock generation. 0d = No PDM clock generation error 1d = PDM clock generation error in selected clock configuration
1	RESET_ON_CLK_STOP_DET_STS	R	0x0	Flag indicating that audio clock source stopped for atleast 1ms. 0d = No audio clock source error 1d = Audio clock source stopped for atleast 1ms
0	RESERVED	R	0x0	Reserved bit; Write only reset value

7.1.55 CLK_ERR_STS1 Register (Address = 0x3D) [Reset = 0x00]

CLK_ERR_STS1 is shown in Figure 7-55 and described in Table 7-56.

Return to the Summary Table.

This register is the clock error and status register 1.

Figure 7-55 CLK_ERR_STS1 Register

7	6	5	4	3	2	1	0
PASI_BCLK_FS_RATIO_ERR	SASI_BCLK_FS_RATIO_ERR	CCLK_FS_RATIO_ERR	PASI_FS_ERR	SASI_FS_ERR	RESERVED
R-0b	R-0b	R-0b	R-0b	R-0b	R-000b

Table 7-56 CLK_ERR_STS1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	PASI_BCLK_FS_RATIO_ERR	R	0x0	Flag indicating PASI bclk fsync ratio error. 0d = No PASI bclk fsync ratio error 1d = PASI bclk fsync ratio error in selected clock configuration
6	SASI_BCLK_FS_RATIO_ERR	R	0x0	Flag indicating SASI bclk fsync ratio error. 0d = No SASI bclk fsync ratio error 1d = SASI bclk fsync ratio error in selected clock configuration
5	CCLK_FS_RATIO_ERR	R	0x0	Flag indicating CCLK fsync ratio error. 0d = No CCLK fsync ratio error 1d = CCLK fsync ratio error
4	PASI_FS_ERR	R	0x0	Flag indicating PASI FS rate change or halt error. 0d = No PASI FS error 1d = PASI FS rate change or halt detected
3	SASI_FS_ERR	R	0x0	Flag indicating SASI FS rate change or halt error. 0d = No SASI FS error 1d = SASI FS rate change or halt detected
2-0	RESERVED	R	0x0	Reserved bits; Write only reset values

7.1.56 CLK_DET_STS0 Register (Address = 0x3E) [Reset = 0x00]

CLK_DET_STS0 is shown in Figure 7-56 and described in Table 7-57.

Return to the Summary Table.

This register is the clock ratio detection register 0.

Figure 7-56 CLK_DET_STS0 Register

7	6	5	4	3	2	1	0
PASI_SAMP_RATE_STS[5:0]						PLL_MODE_STS[1:0]
R-000000b						R-00b

Table 7-57 CLK_DET_STS0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-2	PASI_SAMP_RATE_STS[5:0]	R	0x0	Primary ASI Sample rate detected status. 0d = Reserved 1d = 768000 (670320-791040) 2d = 614400 (536256-632832) 3d = 512000 (446880-527360) 4d = 438857 (383040-452022) 5d = 384000 (335160-395520) 6d = 341333 (297920-351573) 7d = 307200 (268128-316416) 8d = 256000 (223440-263680) 9d = 219429 (191520-226011) 10d = 192000 (167580-197760) 11d = 170667 (148960-175786) 12d = 153600 (134064-158208) 13d = 128000 (111720-131840) 14d = 109714 (95760-113005) 15d = 96000 (83790-98880) 16d = 85333 (74480-87893) 17d = 76800 (67032-79104) 18d = 64000 (55860-65920) 19d = 54857 (47880-56502) 20d = 48000 (41895-49440) 21d = 42667 (37240-43946) 22d = 38400 (33516-39552) 23d = 32000 (27930-32960) 24d = 27429 (23940-28251) 25d = 24000 (20947-24720) 26d = 21333 (18620-21973) 27d = 19200 (16758-19776) 28d = 16000 (13965-16480) 29d = 13714 (11970-14125) 30d = 12000 (10473-12360) 31d = 10667 (9310-10986) 32d = 9600 (8379-9888) 33d = 8000 (6982-8240) 34d = 6857 (5985-7062) 35d = 6000 (5236-6180) 36d = 5333 (4655-5493) 37d = 4800 (4189-4944) 38d = 4000 (3491-4120) 39d = 3429 (2992-3531) 40d = 3000 (2618-3090) 41d-63d = Reserved
1-0	PLL_MODE_STS[1:0]	R	0x0	PLL usage status. 0d = PLL used in integer mode 1d = PLL used in fractional mode 2d = PLL not used 3d = Reserved

7.1.57 CLK_DET_STS1 Register (Address = 0x3F) [Reset = 0x00]

CLK_DET_STS1 is shown in Figure 7-57 and described in Table 7-58.

Return to the Summary Table.

This register is the clock ratio detection register 1.

Figure 7-57 CLK_DET_STS1 Register

7	6	5	4	3	2	1	0
SASI_SAMP_RATE_STS[5:0]						RESERVED
R-000000b						R-00b

Table 7-58 CLK_DET_STS1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-2	SASI_SAMP_RATE_STS[5:0]	R	0x0	Secondary ASI Sample rate detected status. 0d = Reserved 1d = 768000 (670320-791040) 2d = 614400 (536256-632832) 3d = 512000 (446880-527360) 4d = 438857 (383040-452022) 5d = 384000 (335160-395520) 6d = 341333 (297920-351573) 7d = 307200 (268128-316416) 8d = 256000 (223440-263680) 9d = 219429 (191520-226011) 10d = 192000 (167580-197760) 11d = 170667 (148960-175786) 12d = 153600 (134064-158208) 13d = 128000 (111720-131840) 14d = 109714 (95760-113005) 15d = 96000 (83790-98880) 16d = 85333 (74480-87893) 17d = 76800 (67032-79104) 18d = 64000 (55860-65920) 19d = 54857 (47880-56502) 20d = 48000 (41895-49440) 21d = 42667 (37240-43946) 22d = 38400 (33516-39552) 23d = 32000 (27930-32960) 24d = 27429 (23940-28251) 25d = 24000 (20947-24720) 26d = 21333 (18620-21973) 27d = 19200 (16758-19776) 28d = 16000 (13965-16480) 29d = 13714 (11970-14125) 30d = 12000 (10473-12360) 31d = 10667 (9310-10986) 32d = 9600 (8379-9888) 33d = 8000 (6982-8240) 34d = 6857 (5985-7062) 35d = 6000 (5236-6180) 36d = 5333 (4655-5493) 37d = 4800 (4189-4944) 38d = 4000 (3491-4120) 39d = 3429 (2992-3531) 40d = 3000 (2618-3090) 41d-63d = Reserved
1-0	RESERVED	R	0x0	Reserved bits; Write only reset values

7.1.58 CLK_DET_STS2 Register (Address = 0x40) [Reset = 0x00]

CLK_DET_STS2 is shown in Figure 7-58 and described in Table 7-59.

Return to the Summary Table.

This register is the clock ratio detection register 2.

Figure 7-58 CLK_DET_STS2 Register

7	6	5	4	3	2	1	0
RESERVED		FS_CLKSRC_RATIO_DET_MSB_STS[5:0]
R-00b		R-000000b

Table 7-59 CLK_DET_STS2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R	0x0	Reserved bits; Write only reset values
5-0	FS_CLKSRC_RATIO_DET_MSB_STS[5:0]	R	0x0	MSB bits for primary ASI or secondary ASI FSYNC to clock source ratio detected.

7.1.59 CLK_DET_STS3 Register (Address = 0x41) [Reset = 0x00]

CLK_DET_STS3 is shown in Figure 7-59 and described in Table 7-60.

Return to the Summary Table.

This register is the clock ratio detection register 3.

Figure 7-59 CLK_DET_STS3 Register

7	6	5	4	3	2	1	0
FS_CLKSRC_RATIO_DET_LSB_STS[7:0]
R-00000000b

Table 7-60 CLK_DET_STS3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	FS_CLKSRC_RATIO_DET_LSB_STS[7:0]	R	0x0	LSB byte for primary ASI or secondary ASI FSYNC to clock source ratio detected.

7.1.60 INT_CFG Register (Address = 0x42) [Reset = 0x00]

INT_CFG is shown in Figure 7-60 and described in Table 7-61.

Return to the Summary Table.

This regiser is the interrupt configuration register.

Figure 7-60 INT_CFG Register

7	6	5	4	3	2	1	0
INT_POL	INT_EVENT[1:0]		PD_ON_FLT_CFG[1:0]		LTCH_READ_CFG	PD_ON_FLT_RCV_CFG	LTCH_CLR_ON_READ
R/W-0b	R/W-00b		R/W-00b		R/W-0b	R/W-0b	R/W-0b

Table 7-61 INT_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	INT_POL	R/W	0x0	Interrupt polarity. 0b = Active low (IRQZ) 1b = Active high (IRQ)
6-5	INT_EVENT[1:0]	R/W	0x0	Interrupt event configuration. 0d = INT asserts on any unmasked latched interrupts event 1d = INT asserts on any unmasked live interrupts event 2d = INT asserts for 2 ms (typical) for every 4-ms (typical) duration on any unmasked latched interrupts event 3d = INT asserts for 2 ms (typical) one time on each pulse for any unmasked interrupts event
4-3	PD_ON_FLT_CFG[1:0]	R/W	0x0	Powerdown configuration during fault for chx and micbias. 0d = Faults are not considered for power down 1d = Only unmasked faults are considered for power down 2d = All faults are considered for powerdown 3d = Reserved
2	LTCH_READ_CFG	R/W	0x0	Interrupt latch registers readback configuration. 0b = All interrupts can be read through the LTCH registers 1b = Only unmasked interrupts can be read through the LTCH registers
1	PD_ON_FLT_RCV_CFG	R/W	0x0	Configuration for Powerdown ADC channels on fault 0b = Auto recovery, ADC channels are re-powered up when fault goes away 1b = Manual recovery, ADC channels are not re-powered up when fault goes away
0	LTCH_CLR_ON_READ	R/W	0x0	Cfgn for clearing LTCH register bits 0 = LTCH reg bits are cleared on reg read only if live status is zero 1 = LTCH reg bits are cleared on reg read irrespective of live status

7.1.61 DAC_FLT_CFG Register (Address = 0x43) [Reset = 0x50]

DAC_FLT_CFG is shown in Figure 7-61 and described in Table 7-62.

Return to the Summary Table.

This regiser is the interrupt configuration register.

Figure 7-61 DAC_FLT_CFG Register

7	6	5	4	3	2	1	0
RESERVED	DAC_PD_ON_FLT_CFG[1:0]		DAC_PD_ON_FLT_RCV_CFG	OUT_CHx_PD_FLT_STS	DAC_DIS_PD_W_PU	DAC_FLT_DET_DIS	AREG_SC_FLAG_DET_DIS
R-0b	R/W-10b		R/W-1b	R-0b	R/W-0b	R/W-0b	R/W-0b

Table 7-62 DAC_FLT_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0x0	Reserved bit; Write only reset value
6-5	DAC_PD_ON_FLT_CFG[1:0]	R/W	0x2	Powerdown configuration during fault for DAC . 0d = Faults are not considered for power down 1d = Only unmasked faults are considered for power down 2d = All faults are considered for powerdown 3d = Reserved
4	DAC_PD_ON_FLT_RCV_CFG	R/W	0x1	Configuration for Powerdown DAC channels on fault 0b = Auto recovery, DAC channels are re-powered up when fault goes away 1b = Manual recovery, DAC channels are not re-powered up when fault goes away
3	OUT_CHx_PD_FLT_STS	R	0x0	Status for PD on OUTxx faults 0d = No DAC Channel is Powered Down due to fault/s 1d = Some DAC Channel is Powered Down due to fault/s
2	DAC_DIS_PD_W_PU	R/W	0x0	Disable power down on DRVR VG fault while powering up DAC 0b = Power down DAC on DRVR VG fault while power up 1b = Disable power down DAC on DRVR VG fault while power up
1	DAC_FLT_DET_DIS	R/W	0x0	DAC vg_fault/sc_fault detect config 0b = enable 1b = disable
0	AREG_SC_FLAG_DET_DIS	R/W	0x0	AREG short circuit detect config 0b = enable 1b = disable

7.1.62 ADC_DAC_MISC_CFG Register (Address = 0x4B) [Reset = 0x00]

ADC_DAC_MISC_CFG is shown in Figure 7-62 and described in Table 7-63.

Return to the Summary Table.

Option to Mute ADC Channel in Overload Recovery Phase

Figure 7-62 ADC_DAC_MISC_CFG Register

7	6	5	4	3	2	1	0
RESERVED	RESERVED	RESERVED	ADC_CH1_MUTE_ON_OVRLD	ADC_CH2_MUTE_ON_OVRLD	RESERVED
R-0b	R-0b	R-0b	R/W-0b	R/W-0b	R-000b

Table 7-63 ADC_DAC_MISC_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0x0	Reserved bit; Write only reset value
6	RESERVED	R	0x0	Reserved bit; Write only reset value
5	RESERVED	R	0x0	Reserved bit; Write only reset value
4	ADC_CH1_MUTE_ON_OVRLD	R/W	0x0	Mute ADC channel 1 while ADC1 is in Overload Recovery Phase 0b = Disable 1b = Enable
3	ADC_CH2_MUTE_ON_OVRLD	R/W	0x0	Mute ADC channel 2 while ADC2 is in Overload Recovery Phase 0b = Disable 1b = Enable
2-0	RESERVED	R	0x0	Reserved bits; Write only reset values

7.1.63 PWR_TUNE_CFG0 Register (Address = 0x4E) [Reset = 0x00]

PWR_TUNE_CFG0 is shown in Figure 7-63 and described in Table 7-64.

Return to the Summary Table.

This register is configuration register for power tune configuration.

Figure 7-63 PWR_TUNE_CFG0 Register

7	6	5	4	3	2	1	0
ADC_CLK_BY2_MODE	ADC_CIC_ORDER	ADC_FIR_BYPASS	RESERVED		ADC_LOW_PWR_FILT	RESERVED
R/W-0b	R/W-0b	R/W-0b	R-00b		R/W-0b	R-00b

Table 7-64 PWR_TUNE_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	ADC_CLK_BY2_MODE	R/W	0x0	ADC MOD CLK select configuration. 0d = MOD CLK 3MHz 1d = MOD CLK 1.5MHz
6	ADC_CIC_ORDER	R/W	0x0	ADC CIC order configuratoin. 0d = 5th order CIC 1d = 4th order CIC
5	ADC_FIR_BYPASS	R/W	0x0	ADC FIR bypass configuration. 0d = Bypass disable 1d = Bypass enable
4-3	RESERVED	R	0x0	Reserved bits; Write only reset values
2	ADC_LOW_PWR_FILT	R/W	0x0	Low Power filter configuration for ADC 0d = Disable 1d = Enable
1-0	RESERVED	R	0x0	Reserved bits; Write only reset values

7.1.64 PWR_TUNE_CFG1 Register (Address = 0x4F) [Reset = 0x00]

PWR_TUNE_CFG1 is shown in Figure 7-64 and described in Table 7-65.

Return to the Summary Table.

This register is configuration register for power tune configuration.

Figure 7-64 PWR_TUNE_CFG1 Register

7	6	5	4	3	2	1	0
DAC_CLK_BY2_MODE	RESERVED	DAC_FIR_SEG_BYPASS	RESERVED		DAC_LOW_PWR_FILT	DAC_POWER_SCAL	RESERVED
R/W-0b	R-0b	R/W-0b	R-00b		R/W-0b	R/W-0b	R-0b

Table 7-65 PWR_TUNE_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	DAC_CLK_BY2_MODE	R/W	0x0	DAC MOD CLK select configuration. 0d = MOD CLK 3MHz 1d = MOD CLK 1.5MHz
6	RESERVED	R	0x0	Reserved bit; Write only reset value
5	DAC_FIR_SEG_BYPASS	R/W	0x0	DAC FIR and segmenter bypass configuration. 0d = Bypass disable 1d = Bypass enable
4-3	RESERVED	R	0x0	Reserved bits; Write only reset values
2	DAC_LOW_PWR_FILT	R/W	0x0	Low Power Filter configuration for DAC 0d = Disable 1d = Enable
1	DAC_POWER_SCAL	R/W	0x0	DAC IREF select configuration. 0d = Vref/R 1d = Vref/2R
0	RESERVED	R	0x0	Reserved bit; Write only reset value

7.1.65 ADC_CH1_CFG0 Register (Address = 0x50) [Reset = 0x00]

ADC_CH1_CFG0 is shown in Figure 7-65 and described in Table 7-66.

Return to the Summary Table.

This register is configuration register 0 for ADC channel 1.

Figure 7-65 ADC_CH1_CFG0 Register

7	6	5	4	3	2	1	0
ADC_CH1_INSRC[1:0]		RESERVED		RESERVED		ADC_CH1_FULLSCALE_VAL	ADC_CH1_BW_MODE
R/W-00b		R-00b		R-00b		R/W-0b	R/W-0b

Table 7-66 ADC_CH1_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	ADC_CH1_INSRC[1:0]	R/W	0x0	ADC Channel 1 input configuration. 0d = Analog differential input 1d = Analog single-ended input Dont use Dont use
5-4	RESERVED	R	0x0	Reserved bits; Write only reset values
3-2	RESERVED	R	0x0	Reserved bits; Write only reset values
1	ADC_CH1_FULLSCALE_VAL	R/W	0x0	ADC Channel 1 Fullscale value for VREF=2.75 V (applicable for the analog input). 0d = 10 Vrms differential 1d = 5 Vrms differential
0	ADC_CH1_BW_MODE	R/W	0x0	ADC Channel 1 band-width selection. coupling (applicable for the analog input). 0d = audio band-width (24 kHz mode) 1d = wide band-width (96 kHz mode)

7.1.66 ADC_CH1_CFG2 Register (Address = 0x52) [Reset = 0xA1]

ADC_CH1_CFG2 is shown in Figure 7-66 and described in Table 7-67.

Return to the Summary Table.

This register is configuration register 2 for ADC channel 1.

Figure 7-66 ADC_CH1_CFG2 Register

7	6	5	4	3	2	1	0
ADC_CH1_DVOL[7:0]
R/W-10100001b

Table 7-67 ADC_CH1_CFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	ADC_CH1_DVOL[7:0]	R/W	0xA1	Channel 1 digital volume control. 0d = Digital volume is muted 1d = Digital volume control is set to -80 dB 2d = Digital volume control is set to -79.5 dB 3d to 160d = Digital volume control is set as per configuration 161d = Digital volume control is set to 0 dB 162d = Digital volume control is set to 0.5 dB 163d to 253d = Digital volume control is set as per configuration 254d = Digital volume control is set to 46.5 dB 255d = Digital volume control is set to 47 dB

7.1.67 ADC_CH1_CFG3 Register (Address = 0x53) [Reset = 0x80]

ADC_CH1_CFG3 is shown in Figure 7-67 and described in Table 7-68.

Return to the Summary Table.

This register is configuration register 3 for ADC channel 1.

Figure 7-67 ADC_CH1_CFG3 Register

7	6	5	4	3	2	1	0
ADC_CH1_FGAIN[3:0]				RESERVED
R/W-1000b				R-0000b

Table 7-68 ADC_CH1_CFG3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	ADC_CH1_FGAIN[3:0]	R/W	0x8	ADC channel 1 fine gain calibration. 0d = Fine gain is set to -0.8 dB 1d = Fine gain is set to -0.7 dB 2d = Fine gain is set to -0.6 dB 3d to 7d = Fine gain is set as per configuration 8d = Fine gain is set to 0 dB 9d = Fine gain is set to 0.1 dB 10d to 13d = Fine gain is set as per configuration 14d = Fine gain is set to 0.6 dB 15d = Fine gain is set to 0.7 dB
3-0	RESERVED	R	0x0	Reserved bits; Write only reset value

7.1.68 ADC_CH1_CFG4 Register (Address = 0x54) [Reset = 0x00]

ADC_CH1_CFG4 is shown in Figure 7-68 and described in Table 7-69.

Return to the Summary Table.

This register is configuration register 4 for ADC channel 1.

Figure 7-68 ADC_CH1_CFG4 Register

7	6	5	4	3	2	1	0
ADC_CH1_PCAL[5:0]						PCAL_ANA_DIG_SEL[1:0]
R/W-000000b						R/W-00b

Table 7-69 ADC_CH1_CFG4 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-2	ADC_CH1_PCAL[5:0]	R/W	0x0	ADC channel 1 phase calibration with modulator clock resolution. 0d = No phase calibration 1d = Phase calibration delay is set to one cycle of the modulator clock 2d = Phase calibration delay is set to two cycles of the modulator clock 3d to 62d = Phase calibration delay as per configuration 63d = Phase calibration delay is set to 63 cycles of the modulator clock
1-0	PCAL_ANA_DIG_SEL[1:0]	R/W	0x0	PCAL support configuration. 0d = Pcal for both Ana-Dig supported 1d = Pcal for only Ana 2d = Pcal for only Dig 3d = Reserved

7.1.69 ADC_CH2_CFG0 Register (Address = 0x55) [Reset = 0x00]

ADC_CH2_CFG0 is shown in Figure 7-69 and described in Table 7-70.

Return to the Summary Table.

This register is configuration register 0 for ADC channel 2.

Figure 7-69 ADC_CH2_CFG0 Register

7	6	5	4	3	2	1	0
ADC_CH2_INSRC[1:0]		RESERVED		ADC_CH2_CM_TOL[1:0]		ADC_CH2_FULLSCALE_VAL	ADC_CH2_BW_MODE
R/W-00b		R-00b		R/W-00b		R/W-0b	R/W-0b

Table 7-70 ADC_CH2_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	ADC_CH2_INSRC[1:0]	R/W	0x0	ADC Channel 2 input configuration. 0d = Analog differential input 1d = Analog single-ended input Dont use Dont use
5-4	RESERVED	R	0x0	Reserved bits; Write only reset values
3-2	ADC_CH2_CM_TOL[1:0]	R/W	0x0	ADC Channel 2 input coupling (applicable for the analog input). 0d = AC-coupled input with common mode variance tolerance supported 50 mVpp for single ended and 100 mVpp for differential configuration 1d = AC-coupled / DC-coupled input with common mode variance tolerance supported 500 mVpp for single ended and 1 Vpp for differential configuration (Expected SNR degradation of 1-2 dB) 2d = AC-coupled / DC-coupled input with common mode variance tolerance supported rail to rail (supply to ground) (Expected SNR degradation of 3-4 dB , High CMRR supported only in this case) 3d = Reserved
1	ADC_CH2_FULLSCALE_VAL	R/W	0x0	ADC Channel 2 Fullscale value for VREF=2.75 V (applicable for the analog input). 0d = 10 Vrms differential 1d = 5 Vrms differential
0	ADC_CH2_BW_MODE	R/W	0x0	ADC Channel 2 band-width selection. coupling (applicable for the analog input). 0d = audio band-width (24 kHz mode) 1d = wide band-width (96 kHz mode) (Supported only for 40-kΩ input impedance case)

7.1.70 ADC_CH2_CFG2 Register (Address = 0x57) [Reset = 0xA1]

ADC_CH2_CFG2 is shown in Figure 7-70 and described in Table 7-71.

Return to the Summary Table.

This register is configuration register 2 for channel 2.

Figure 7-70 ADC_CH2_CFG2 Register

7	6	5	4	3	2	1	0
ADC_CH2_DVOL[7:0]
R/W-10100001b

Table 7-71 ADC_CH2_CFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	ADC_CH2_DVOL[7:0]	R/W	0xA1	Channel 1 digital volume control. 0d = Digital volume is muted 1d = Digital volume control is set to -80 dB 2d = Digital volume control is set to -79.5 dB 3d to 160d = Digital volume control is set as per configuration 161d = Digital volume control is set to 0 dB 162d = Digital volume control is set to 0.5 dB 163d to 253d = Digital volume control is set as per configuration 254d = Digital volume control is set to 46.5 dB 255d = Digital volume control is set to 47 dB

7.1.71 ADC_CH2_CFG3 Register (Address = 0x58) [Reset = 0x80]

ADC_CH2_CFG3 is shown in Figure 7-71 and described in Table 7-72.

Return to the Summary Table.

This register is configuration register 3 for ADC Channel 2.

Figure 7-71 ADC_CH2_CFG3 Register

7	6	5	4	3	2	1	0
ADC_CH2_FGAIN[3:0]				RESERVED
R/W-1000b				R-0000b

Table 7-72 ADC_CH2_CFG3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	ADC_CH2_FGAIN[3:0]	R/W	0x8	ADC Channel 2 fine gain calibration. 0d = Fine gain is set to -0.8 dB 1d = Fine gain is set to -0.7 dB 2d = Fine gain is set to -0.6 dB 3d to 7d = Fine gain is set as per configuration 8d = Fine gain is set to 0 dB 9d = Fine gain is set to 0.1 dB 10d to 13d = Fine gain is set as per configuration 14d = Fine gain is set to 0.6 dB 15d = Fine gain is set to 0.7 dB
3-0	RESERVED	R	0x0	Reserved bits; Write only reset value

7.1.72 ADC_CH2_CFG4 Register (Address = 0x59) [Reset = 0x00]

ADC_CH2_CFG4 is shown in Figure 7-72 and described in Table 7-73.

Return to the Summary Table.

This register is configuration register 4 for ADC Channel 2.

Figure 7-72 ADC_CH2_CFG4 Register

7	6	5	4	3	2	1	0
ADC_CH2_PCAL[5:0]						RESERVED
R/W-000000b						R-00b

Table 7-73 ADC_CH2_CFG4 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-2	ADC_CH2_PCAL[5:0]	R/W	0x0	ADC Channel 2 phase calibration with modulator clock resolution. 0d = No phase calibration 1d = Phase calibration delay is set to one cycle of the modulator clock 2d = Phase calibration delay is set to two cycles of the modulator clock 3d to 62d = Phase calibration delay as per configuration 63d = Phase calibration delay is set to 63 cycles of the modulator clock
1-0	RESERVED	R	0x0	Reserved bits; Write only reset value

7.1.73 ADC_CH3_CFG0 Register (Address = 0x5A) [Reset = 0x00]

ADC_CH3_CFG0 is shown in Figure 7-73 and described in Table 7-74.

Return to the Summary Table.

This register is configuration register 0 for ADC channel 3.

Figure 7-73 ADC_CH3_CFG0 Register

7	6	5	4	3	2	1	0
ADC_CH3_CLONE	RESERVED
R/W-0b	R-0000000b

Table 7-74 ADC_CH3_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	ADC_CH3_CLONE	R/W	0x0	ADC Channel 3 input configuration. 0d = clone disabled 1d = Channel 3 Digital Filter Input is generated same as Channel 1 Digital Filter Input (Cloned Input)
6-0	RESERVED	R	0x0	Reserved bits; Write only reset value

7.1.74 ADC_CH3_CFG2 Register (Address = 0x5B) [Reset = 0xA1]

ADC_CH3_CFG2 is shown in Figure 7-74 and described in Table 7-75.

Return to the Summary Table.

This register is configuration register 2 for ADC channel 3.

Figure 7-74 ADC_CH3_CFG2 Register

7	6	5	4	3	2	1	0
ADC_CH3_DVOL[7:0]
R/W-10100001b

Table 7-75 ADC_CH3_CFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	ADC_CH3_DVOL[7:0]	R/W	0xA1	Channel 3 digital volume control. 0d = Digital volume is muted 1d = Digital volume control is set to -80 dB 2d = Digital volume control is set to -79.5 dB 3d to 160d = Digital volume control is set as per configuration 161d = Digital volume control is set to 0 dB 162d = Digital volume control is set to 0.5 dB 163d to 253d = Digital volume control is set as per configuration 254d = Digital volume control is set to 46.5 dB 255d = Digital volume control is set to 47 dB

7.1.75 ADC_CH3_CFG3 Register (Address = 0x5C) [Reset = 0x80]

ADC_CH3_CFG3 is shown in Figure 7-75 and described in Table 7-76.

Return to the Summary Table.

This register is configuration register 3 for ADC channel 3.

Figure 7-75 ADC_CH3_CFG3 Register

7	6	5	4	3	2	1	0
ADC_CH3_FGAIN[3:0]				RESERVED
R/W-1000b				R-0000b

Table 7-76 ADC_CH3_CFG3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	ADC_CH3_FGAIN[3:0]	R/W	0x8	ADC channel 3 fine gain calibration. 0d = Fine gain is set to -0.8 dB 1d = Fine gain is set to -0.7 dB 2d = Fine gain is set to -0.6 dB 3d to 7d = Fine gain is set as per configuration 8d = Fine gain is set to 0 dB 9d = Fine gain is set to 0.1 dB 10d to 13d = Fine gain is set as per configuration 14d = Fine gain is set to 0.6 dB 15d = Fine gain is set to 0.7 dB
3-0	RESERVED	R	0x0	Reserved bits; Write only reset value

7.1.76 ADC_CH3_CFG4 Register (Address = 0x5D) [Reset = 0x00]

ADC_CH3_CFG4 is shown in Figure 7-76 and described in Table 7-77.

Return to the Summary Table.

This register is configuration register 4 for ADC channel 3.

Figure 7-76 ADC_CH3_CFG4 Register

7	6	5	4	3	2	1	0
ADC_CH3_PCAL[5:0]						RESERVED
R/W-000000b						R-00b

Table 7-77 ADC_CH3_CFG4 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-2	ADC_CH3_PCAL[5:0]	R/W	0x0	ADC channel 3 phase calibration with modulator clock resolution. 0d = No phase calibration 1d = Phase calibration delay is set to one cycle of the modulator clock 2d = Phase calibration delay is set to two cycles of the modulator clock 3d to 62d = Phase calibration delay as per configuration 63d = Phase calibration delay is set to 63 cycles of the modulator clock
1-0	RESERVED	R	0x0	Reserved bits; Write only reset value

7.1.77 ADC_CH4_CFG0 Register (Address = 0x5E) [Reset = 0x00]

ADC_CH4_CFG0 is shown in Figure 7-77 and described in Table 7-78.

Return to the Summary Table.

This register is configuration register 0 for ADC Channel 4.

Figure 7-77 ADC_CH4_CFG0 Register

7	6	5	4	3	2	1	0
ADC_CH4_CLONE	RESERVED
R/W-0b	R-0000000b

Table 7-78 ADC_CH4_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	ADC_CH4_CLONE	R/W	0x0	ADC Channel 4 input configuration. 0d = clone disabled 1d = Channel 4 Digital Filter Input is generated same as Channel 2 Digital Filter Input (Cloned Input)
6-0	RESERVED	R	0x0	Reserved bits; Write only reset value

7.1.78 ADC_CH4_CFG2 Register (Address = 0x5F) [Reset = 0xA1]

ADC_CH4_CFG2 is shown in Figure 7-78 and described in Table 7-79.

Return to the Summary Table.

This register is configuration register 2 for channel 4.

Figure 7-78 ADC_CH4_CFG2 Register

7	6	5	4	3	2	1	0
ADC_CH4_DVOL[7:0]
R/W-10100001b

Table 7-79 ADC_CH4_CFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	ADC_CH4_DVOL[7:0]	R/W	0xA1	Channel 4 digital volume control. 0d = Digital volume is muted 1d = Digital volume control is set to -80 dB 2d = Digital volume control is set to -79.5 dB 3d to 160d = Digital volume control is set as per configuration 161d = Digital volume control is set to 0 dB 162d = Digital volume control is set to 0.5 dB 163d to 253d = Digital volume control is set as per configuration 254d = Digital volume control is set to 46.5 dB 255d = Digital volume control is set to 47 dB

7.1.79 ADC_CH4_CFG3 Register (Address = 0x60) [Reset = 0x80]

ADC_CH4_CFG3 is shown in Figure 7-79 and described in Table 7-80.

Return to the Summary Table.

This register is configuration register 3 for ADC Channel 4.

Figure 7-79 ADC_CH4_CFG3 Register

7	6	5	4	3	2	1	0
ADC_CH4_FGAIN[3:0]				RESERVED
R/W-1000b				R-0000b

Table 7-80 ADC_CH4_CFG3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	ADC_CH4_FGAIN[3:0]	R/W	0x8	ADC Channel 4 fine gain calibration. 0d = Fine gain is set to -0.8 dB 1d = Fine gain is set to -0.7 dB 2d = Fine gain is set to -0.6 dB 3d to 7d = Fine gain is set as per configuration 8d = Fine gain is set to 0 dB 9d = Fine gain is set to 0.1 dB 10d to 13d = Fine gain is set as per configuration 14d = Fine gain is set to 0.6 dB 15d = Fine gain is set to 0.7 dB
3-0	RESERVED	R	0x0	Reserved bits; Write only reset value

7.1.80 ADC_CH4_CFG4 Register (Address = 0x61) [Reset = 0x00]

ADC_CH4_CFG4 is shown in Figure 7-80 and described in Table 7-81.

Return to the Summary Table.

This register is configuration register 4 for ADC Channel 4.

Figure 7-80 ADC_CH4_CFG4 Register

7	6	5	4	3	2	1	0
ADC_CH4_PCAL[5:0]						RESERVED
R/W-000000b						R-00b

Table 7-81 ADC_CH4_CFG4 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-2	ADC_CH4_PCAL[5:0]	R/W	0x0	ADC Channel 4 phase calibration with modulator clock resolution. 0d = No phase calibration 1d = Phase calibration delay is set to one cycle of the modulator clock 2d = Phase calibration delay is set to two cycles of the modulator clock 3d to 62d = Phase calibration delay as per configuration 63d = Phase calibration delay is set to 63 cycles of the modulator clock
1-0	RESERVED	R	0x0	Reserved bits; Write only reset value

7.1.81 OUT1x_CFG0 Register (Address = 0x64) [Reset = 0x20]

OUT1x_CFG0 is shown in Figure 7-81 and described in Table 7-82.

Return to the Summary Table.

This register is configuration register 0 for Channel OUT1x.

Figure 7-81 OUT1x_CFG0 Register

7	6	5	4	3	2	1	0
OUT1x_SRC[2:0]			OUT1x_CFG[2:0]			OUT1x_VCOM	OUT1x_LP_MODE
R/W-001b			R/W-000b			R/W-0b	R/W-0b

Table 7-82 OUT1x_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-5	OUT1x_SRC[2:0]	R/W	0x1	OUT1x Source Configuration. 0d = Output driver disabled 1d = Input from DAC signal chain 2d = Input from Analog bypass path 3d = Input from both DAC signal chain and Analog bypass path 4d = Independent input from both DAC signal chain and Analog bypass path (DAC -> OUT1P , IN1P -> OUT1M) 5d = Independent input from both DAC signal chain and Analog bypass path (IN1M -> OUT1P, DAC -> OUT1M) 6d-7d = Reserved; Don't use
4-2	OUT1x_CFG[2:0]	R/W	0x0	OUT1x DAC / Analog Bypass Routing Configuration. (Don't use if OUT1x_SRC configured 4d or 5d) 0d = Differential (DAC1AP + DAC1BP / IN1M -> OUT1P ; DAC1AM + DAC1BM / IN1P -> OUT1M) 1d = Stereo single-ended (DAC1A / IN1M -> OUT1P ; DAC1B / IN1P -> OUT1M) 2d = Mono single-ended with output at OUT1P only (DAC1A + DAC1B / IN1M-> OUT1P) 3d = Mono single-ended with output at OUT1M only (DAC1A + DAC1B / IN1P -> OUT1M) 4d = Pseudo differential with OUT1M as VCOM (DAC1A, DAC1B / IN1M -> OUT1P, VCOM -> OUT1M) 5d = Pseudo differential with OUT1M as VCOM and OUT2M for external sensing (DAC1A, DAC1B / IN1M -> OUT1P, VCOM -> OUT1M) 6d = Pseudo differential with OUT1P as VCOM (IN1P -> OUT1M, VCOM -> OUT1P) 7d = Reserved; Don't use
1	OUT1x_VCOM	R/W	0x0	Channel OUT1x VCOM configuration. 0d = 0.6 * Vref (for 1.375V VREF mode alone as 0.654*Vref) 1d = AVDD by 2
0	OUT1x_LP_MODE	R/W	0x0	Low power mode of OUT1x channel. (only valid for OUT1x_SRC configured as DAC signal chain) (not valid for OUT1x_CFG configured as Stereo SE) 0d = Low power mode is disabled (3 dB higher perf) 1d = Low power mode is enabled

7.1.82 OUT1x_CFG1 Register (Address = 0x65) [Reset = 0x20]

OUT1x_CFG1 is shown in Figure 7-82 and described in Table 7-83.

Return to the Summary Table.

This register is configuration register 1 for Channel OUT1x.

Figure 7-82 OUT1x_CFG1 Register

7	6	5	4	3	2	1	0
OUT1P_DRIVE[1:0]		OUT1P_LVL_CTRL[2:0]			RESERVED	RESERVED	DAC_CH1_BW_MODE
R/W-00b		R/W-100b			R-0b	R-0b	R/W-0b

Table 7-83 OUT1x_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	OUT1P_DRIVE[1:0]	R/W	0x0	Channel OUT1P drive configuration. 0d = Line out driver with minimum 300 Ω impedance 1d = Headphone driver with minimum 4 Ω impedance 2d = 4 Ω 3d = FD Receiver/Debug
5-3	OUT1P_LVL_CTRL[2:0]	R/W	0x4	Channel OUT1P level control configuration Dont use Dont use Dont use Dont use 4d = -8 dB 5d = -14 dB 6d = -20 dB 7d = -26 dB
2	RESERVED	R	0x0	Reserved bit; Write only reset value
1	RESERVED	R	0x0	Reserved bit; Write only reset value
0	DAC_CH1_BW_MODE	R/W	0x0	DAC Channel 1 band-width selection. 0d = audio band-width (24 kHz mode) 1d = wide band-width (96 kHz mode)

7.1.83 OUT1x_CFG2 Register (Address = 0x66) [Reset = 0x20]

OUT1x_CFG2 is shown in Figure 7-83 and described in Table 7-84.

Return to the Summary Table.

This register is configuration register 2 for Channel OUT2x.

Figure 7-83 OUT1x_CFG2 Register

7	6	5	4	3	2	1	0
OUT1M_DRIVE[1:0]		OUT1M_LVL_CTRL[2:0]			RESERVED	DAC_CH1_FULLSCALE_VAL	DAC_CH1_CM_TOL
R/W-00b		R/W-100b			R-0b	R/W-0b	R/W-0b

Table 7-84 OUT1x_CFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	OUT1M_DRIVE[1:0]	R/W	0x0	Channel OUT1M drive configuration. 0d = Line out driver with minimum 300 Ω impedance 1d = Headphone driver with minimum 4 Ω impedance 2d = 4 Ω 3d = FD Receiver/Debug
5-3	OUT1M_LVL_CTRL[2:0]	R/W	0x4	Channel OUT1M level control configuration. Dont use Dont use Dont use Dont use 4d = -8 dB 5d = -14 dB 6d = -20 dB 7d = -26 dB
2	RESERVED	R	0x0	Reserved bit; Write only reset value
1	DAC_CH1_FULLSCALE_VAL	R/W	0x0	DAC Channel 1 Fullscale value for VREF=2.75 V 0d = 10 Vrms differential 1d = 5 Vrms differential
0	DAC_CH1_CM_TOL	R/W	0x0	DAC Channel 1 input coupling (applicable for the analog input). 0d = AC-coupled input with common mode variance tolerance supported 50 mVpp for single ended and 100 mVpp for differential configuration 1d = AC-coupled / DC-coupled input with common mode variance tolerance supported rail to rail (supply to ground) (Expected SNR degradation of 3-4 dB , High CMRR supported only in this case)

7.1.84 DAC_CH1A_CFG0 Register (Address = 0x67) [Reset = 0xC9]

DAC_CH1A_CFG0 is shown in Figure 7-84 and described in Table 7-85.

Return to the Summary Table.

This register is configuration register 0 for DAC channel 1A.

Figure 7-84 DAC_CH1A_CFG0 Register

7	6	5	4	3	2	1	0
DAC_CH1A_DVOL[7:0]
R/W-11001001b

Table 7-85 DAC_CH1A_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	DAC_CH1A_DVOL[7:0]	R/W	0xC9	Channel 1A digital volume control. 0d = Digtial Volume is muted 1d = Digital Volume Control set to -100 dB 2d = Digital Volume Control set to -99.5 dB 3d to 200d = Digital Volume Control set to as per configuration 201d = Digital Volume Control set to 0 dB 202d = Digital Volume Control set to +0.5 dB 203d to 253d = Digital Volume Control set to as per configuration 254d = Digital Volume Control set to +26.5 dB 255d = Digital Volume Control set to +27 dB

7.1.85 DAC_CH1A_CFG1 Register (Address = 0x68) [Reset = 0x80]

DAC_CH1A_CFG1 is shown in Figure 7-85 and described in Table 7-86.

Return to the Summary Table.

This register is configuration register 1 for DAC channel 1A.

Figure 7-85 DAC_CH1A_CFG1 Register

7	6	5	4	3	2	1	0
DAC_CH1A_FGAIN[3:0]				RESERVED
R/W-1000b				R-0000b

Table 7-86 DAC_CH1A_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	DAC_CH1A_FGAIN[3:0]	R/W	0x8	DAC channel 1A fine gain calibration. 0d = Fine gain is set to -0.8 dB 1d = Fine gain is set to -0.7 dB 2d = Fine gain is set to -0.6 dB 3d to 7d = Fine gain is set as per configuration 8d = Fine gain is set to 0 dB 9d = Fine gain is set to 0.1 dB 10d to 13d = Fine gain is set as per configuration 14d = Fine gain is set to 0.6 dB 15d = Fine gain is set to 0.7 dB
3-0	RESERVED	R	0x0	Reserved bits; Write only reset value

7.1.86 DAC_CH1B_CFG0 Register (Address = 0x69) [Reset = 0xC9]

DAC_CH1B_CFG0 is shown in Figure 7-86 and described in Table 7-87.

Return to the Summary Table.

This register is configuration register 0 for DAC channel 1B.

Figure 7-86 DAC_CH1B_CFG0 Register

7	6	5	4	3	2	1	0
DAC_CH1B_DVOL[7:0]
R/W-11001001b

Table 7-87 DAC_CH1B_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	DAC_CH1B_DVOL[7:0]	R/W	0xC9	Channel 1B digital volume control. 0d = Digtial Volume is muted 1d = Digital Volume Control set to -100 dB 2d = Digital Volume Control set to -99.5 dB 3d to 200d = Digital Volume Control set to as per configuration 201d = Digital Volume Control set to 0 dB 202d = Digital Volume Control set to +0.5 dB 203d to 253d = Digital Volume Control set to as per configuration 254d = Digital Volume Control set to +26.5 dB 255d = Digital Volume Control set to +27 dB

7.1.87 DAC_CH1B_CFG1 Register (Address = 0x6A) [Reset = 0x80]

DAC_CH1B_CFG1 is shown in Figure 7-87 and described in Table 7-88.

Return to the Summary Table.

This register is configuration register 1 for DAC channel 1B.

Figure 7-87 DAC_CH1B_CFG1 Register

7	6	5	4	3	2	1	0
DAC_CH1B_FGAIN[3:0]				RESERVED
R/W-1000b				R-0000b

Table 7-88 DAC_CH1B_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	DAC_CH1B_FGAIN[3:0]	R/W	0x8	DAC channel 1B fine gain calibration. 0d = Fine gain is set to -0.8 dB 1d = Fine gain is set to -0.7 dB 2d = Fine gain is set to -0.6 dB 3d to 7d = Fine gain is set as per configuration 8d = Fine gain is set to 0 dB 9d = Fine gain is set to 0.1 dB 10d to 13d = Fine gain is set as per configuration 14d = Fine gain is set to 0.6 dB 15d = Fine gain is set to 0.7 dB
3-0	RESERVED	R	0x0	Reserved bits; Write only reset value

7.1.88 OUT2x_CFG0 Register (Address = 0x6B) [Reset = 0x20]

OUT2x_CFG0 is shown in Figure 7-88 and described in Table 7-89.

Return to the Summary Table.

This register is configuration register 0 for Channel OUT2x.

Figure 7-88 OUT2x_CFG0 Register

7	6	5	4	3	2	1	0
OUT2x_SRC[2:0]			OUT2x_CFG[2:0]			OUT2x_VCOM	OUT2x_LP_MODE
R/W-001b			R/W-000b			R/W-0b	R/W-0b

Table 7-89 OUT2x_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-5	OUT2x_SRC[2:0]	R/W	0x1	OUT2x Source Configuration. 0d = Output driver disabled 1d = Input from DAC signal chain 2d = Input from Analog bypass path 3d = Input from both DAC signal chain and Analog bypass path 4d = Independent input from both DAC signal chain and Analog bypass path (DAC -> OUT2P , IN2P -> OUT2M) 5d = Independent input from both DAC signal chain and Analog bypass path (IN2M -> OUT2P, DAC -> OUT2M) 6d-7d = Reserved; Don't use
4-2	OUT2x_CFG[2:0]	R/W	0x0	OUT2x DAC / Analog Bypass Routing Configuration. (Don't use if OUT1x_SRC configured 4d or 5d) 0d = Differential (DAC2AP + DAC2BP / IN2M -> OUT2P ; DAC2AM + DAC2BM / IN2P -> OUT2M) 1d = Stereo single-ended (DAC2A / IN2M -> OUT2P ; DAC2B / IN2P -> OUT2M) 2d = Mono single-ended with output at OUT2P only (DAC2A + DAC2B / IN2M-> OUT2P) 3d = Mono single-ended with output at OUT2M only (DAC2A + DAC2B / IN2P -> OUT2M) 4d = Pseudo differential with OUT2M as VCOM (DAC2A, DAC2B / IN2M -> OUT2P, VCOM -> OUT2M) 5d =Reserved; Don't use 6d = Pseudo differential with OUT2P as VCOM (IN2P -> OUT2M, VCOM -> OUT2P) 7d = Reserved; Don't use
1	OUT2x_VCOM	R/W	0x0	Channel OUT2x VCOM configuration. 0d = 0.6 * Vref (for 1.375V VREF mode alone as 0.654*Vref) 2d = AVDD by 2
0	OUT2x_LP_MODE	R/W	0x0	Low power mode of OUT2x channel. (only valid for OUT2x_SRC configured as DAC signal chain) (not valid for OUT2x_CFG configured as Stereo SE) 0d = Low power mode is disabled (3 dB higher perf) 1d = Low power mode is enabled

7.1.89 OUT2x_CFG1 Register (Address = 0x6C) [Reset = 0x20]

OUT2x_CFG1 is shown in Figure 7-89 and described in Table 7-90.

Return to the Summary Table.

This register is configuration register 1 for Channel OUT2x.

Figure 7-89 OUT2x_CFG1 Register

7	6	5	4	3	2	1	0
OUT2P_DRIVE[1:0]		OUT2P_LVL_CTRL[2:0]			RESERVED	RESERVED	DAC_CH2_BW_MODE
R/W-00b		R/W-100b			R-0b	R-0b	R/W-0b

Table 7-90 OUT2x_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	OUT2P_DRIVE[1:0]	R/W	0x0	Channel OUT2P drive configuration. 0d = Line out driver with minimum 300 Ω impedance 1d = Headphone driver with minimum 4 Ω impedance 2d = 4 Ω 3d = FD Receiver/Debug
5-3	OUT2P_LVL_CTRL[2:0]	R/W	0x4	Channel OUT2P level control configuration. Dont use Dont use Dont use Dont use 4d = -8 dB 5d = -14 dB 6d = -20 dB 7d = -26 dB
2	RESERVED	R	0x0	Reserved bit; Write only reset value
1	RESERVED	R	0x0	Reserved bit; Write only reset value
0	DAC_CH2_BW_MODE	R/W	0x0	DAC Channel 2 band-width selection. 0d = audio band-width (24 kHz mode) 1d = wide band-width (96 kHz mode)

7.1.90 OUT2x_CFG2 Register (Address = 0x6D) [Reset = 0x20]

OUT2x_CFG2 is shown in Figure 7-90 and described in Table 7-91.

Return to the Summary Table.

This register is configuration register 2 for Channel OUT2x.

Figure 7-90 OUT2x_CFG2 Register

7	6	5	4	3	2	1	0
OUT2M_DRIVE[1:0]		OUT2M_LVL_CTRL[2:0]			RESERVED	DAC_CH2_FULLSCALE_VAL	DAC_CH2_CM_TOL
R/W-00b		R/W-100b			R-0b	R/W-0b	R/W-0b

Table 7-91 OUT2x_CFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	OUT2M_DRIVE[1:0]	R/W	0x0	Channel OUT2M drive configuration. 0d = Line out driver with minimum 300 Ω impedance 1d = Headphone driver with minimum 4 Ω impedance 2d = 4 Ω 3d = FD Receiver/Debug
5-3	OUT2M_LVL_CTRL[2:0]	R/W	0x4	Channel OUT2M level control configuration. Dont use Dont use Dont use Dont use 4d = -8 dB 5d = -14 dB 6d = -20 dB 7d = -26 dB
2	RESERVED	R	0x0	Reserved bit; Write only reset value
1	DAC_CH2_FULLSCALE_VAL	R/W	0x0	DAC Channel 2 Fullscale value for VREF=2.75 V 0d = 10 Vrms differential 1d = 5 Vrms differential
0	DAC_CH2_CM_TOL	R/W	0x0	DAC Channel 2 input coupling (applicable for the analog input). 0d = AC-coupled input with common mode variance tolerance supported 50 mVpp for single ended and 100 mVpp for differential configuration 1d = AC-coupled / DC-coupled input with common mode variance tolerance supported rail to rail (supply to ground) (Expected SNR degradation of 3-4 dB , High CMRR supported only in this case)

7.1.91 DAC_CH2A_CFG0 Register (Address = 0x6E) [Reset = 0xC9]

DAC_CH2A_CFG0 is shown in Figure 7-91 and described in Table 7-92.

Return to the Summary Table.

This register is configuration register 0 for DAC channel 2A.

Figure 7-91 DAC_CH2A_CFG0 Register

7	6	5	4	3	2	1	0
DAC_CH2A_DVOL[7:0]
R/W-11001001b

Table 7-92 DAC_CH2A_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	DAC_CH2A_DVOL[7:0]	R/W	0xC9	Channel 2A digital volume control. 0d = Digtial Volume is muted 1d = Digital Volume Control set to -100 dB 2d = Digital Volume Control set to -99.5 dB 3d to 200d = Digital Volume Control set to as per configuration 201d = Digital Volume Control set to 0 dB 202d = Digital Volume Control set to +0.5 dB 203d to 253d = Digital Volume Control set to as per configuration 254d = Digital Volume Control set to +26.5 dB 255d = Digital Volume Control set to +27 dB

7.1.92 DAC_CH2A_CFG1 Register (Address = 0x6F) [Reset = 0x80]

DAC_CH2A_CFG1 is shown in Figure 7-92 and described in Table 7-93.

Return to the Summary Table.

This register is configuration register 1 for DAC channel 2A.

Figure 7-92 DAC_CH2A_CFG1 Register

7	6	5	4	3	2	1	0
DAC_CH2A_FGAIN[3:0]				RESERVED
R/W-1000b				R-0000b

Table 7-93 DAC_CH2A_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	DAC_CH2A_FGAIN[3:0]	R/W	0x8	DAC channel 2A fine gain calibration. 0d = Fine gain is set to -0.8 dB 1d = Fine gain is set to -0.7 dB 2d = Fine gain is set to -0.6 dB 3d to 7d = Fine gain is set as per configuration 8d = Fine gain is set to 0 dB 9d = Fine gain is set to 0.1 dB 10d to 13d = Fine gain is set as per configuration 14d = Fine gain is set to 0.6 dB 15d = Fine gain is set to 0.7 dB
3-0	RESERVED	R	0x0	Reserved bits; Write only reset value

7.1.93 DAC_CH2B_CFG0 Register (Address = 0x70) [Reset = 0xC9]

DAC_CH2B_CFG0 is shown in Figure 7-93 and described in Table 7-94.

Return to the Summary Table.

This register is configuration register 0 for DAC channel 2B.

Figure 7-93 DAC_CH2B_CFG0 Register

7	6	5	4	3	2	1	0
DAC_CH2B_DVOL[7:0]
R/W-11001001b

Table 7-94 DAC_CH2B_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	DAC_CH2B_DVOL[7:0]	R/W	0xC9	Channel 2B digital volume control. 0d = Digtial Volume is muted 1d = Digital Volume Control set to -100 dB 2d = Digital Volume Control set to -99.5 dB 3d to 200d = Digital Volume Control set to as per configuration 201d = Digital Volume Control set to 0 dB 202d = Digital Volume Control set to +0.5 dB 203d to 253d = Digital Volume Control set to as per configuration 254d = Digital Volume Control set to +26.5 dB 255d = Digital Volume Control set to +27 dB

7.1.94 DAC_CH2B_CFG1 Register (Address = 0x71) [Reset = 0x80]

DAC_CH2B_CFG1 is shown in Figure 7-94 and described in Table 7-95.

Return to the Summary Table.

This register is configuration register 1 for DAC channel 2B.

Figure 7-94 DAC_CH2B_CFG1 Register

7	6	5	4	3	2	1	0
DAC_CH2B_FGAIN[3:0]				RESERVED
R/W-1000b				R-0000b

Table 7-95 DAC_CH2B_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	DAC_CH2B_FGAIN[3:0]	R/W	0x8	DAC channel 2B fine gain calibration. 0d = Fine gain is set to -0.8 dB 1d = Fine gain is set to -0.7 dB 2d = Fine gain is set to -0.6 dB 3d to 7d = Fine gain is set as per configuration 8d = Fine gain is set to 0 dB 9d = Fine gain is set to 0.1 dB 10d to 13d = Fine gain is set as per configuration 14d = Fine gain is set to 0.6 dB 15d = Fine gain is set to 0.7 dB
3-0	RESERVED	R	0x0	Reserved bits; Write only reset value

7.1.95 DSP_CFG0 Register (Address = 0x72) [Reset = 0x18]

DSP_CFG0 is shown in Figure 7-95 and described in Table 7-96.

Return to the Summary Table.

This register is the digital signal processor (DSP) configuration register 0.

Figure 7-95 DSP_CFG0 Register

7	6	5	4	3	2	1	0
ADC_DSP_DECI_FILT[1:0]		ADC_DSP_HPF_SEL[1:0]		ADC_DSP_BQ_CFG[1:0]		ADC_DSP_DISABLE_SOFT_STEP	ADC_DSP_DVOL_GANG
R/W-00b		R/W-01b		R/W-10b		R/W-0b	R/W-0b

Table 7-96 DSP_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	ADC_DSP_DECI_FILT[1:0]	R/W	0x0	ADC channel decimation filter response. 0d = Linear phase 1d = Low latency 2d = Ultra-low latency 3d = Reserved; Don't use
5-4	ADC_DSP_HPF_SEL[1:0]	R/W	0x1	ADC channel high-pass filter (HPF) selection. 0d = Programmable first-order IIR filter for a custom HPF with default coefficient values in P10_R120-127 and P11_R8-11 set as the all-pass filter 1d = HPF with a cutoff of 0.00002 x f_S (1 Hz at f_S = 48 kHz) is selected 2d = HPF with a cutoff of 0.00025 x f_S (12 Hz at f_S = 48 kHz) is selected 3d = HPF with a cutoff of 0.002 x f_S (96 Hz at f_S = 48 kHz) is selected
3-2	ADC_DSP_BQ_CFG[1:0]	R/W	0x2	Number of biquads per ADC channel configuration. 0d = No biquads per channel; biquads are all disabled 1d = 1 biquad per channel 2d = 2 biquads per channel 3d = 3 biquads per channel
1	ADC_DSP_DISABLE_SOFT_STEP	R/W	0x0	ADC Soft-stepping disable during DVOL change, mute, and unmute. 0d = Soft-stepping enabled 1d = Soft-stepping disabled
0	ADC_DSP_DVOL_GANG	R/W	0x0	DVOL control ganged across ADC channels. 0d = Each channel has its own DVOL CTRL settings as programmed in the ADC_CHx_DVOL bits 1d = All active channels must use the channel 1 DVOL setting (ADC_CH1_DVOL) irrespective of whether channel 1 is turned on or not

7.1.96 DSP_CFG1 Register (Address = 0x73) [Reset = 0x18]

DSP_CFG1 is shown in Figure 7-96 and described in Table 7-97.

Return to the Summary Table.

This register is the digital signal processor (DSP) configuration register 0.

Figure 7-96 DSP_CFG1 Register

7	6	5	4	3	2	1	0
DAC_DSP_INTX_FILT[1:0]		DAC_DSP_HPF_SEL[1:0]		DAC_DSP_BQ_CFG[1:0]		DAC_DSP_DISABLE_SOFT_STEP	DAC_DSP_DVOL_GANG
R/W-00b		R/W-01b		R/W-10b		R/W-0b	R/W-0b

Table 7-97 DSP_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	DAC_DSP_INTX_FILT[1:0]	R/W	0x0	DAC channel decimation filter response. 0d = Linear phase 1d = Low latency 2d = Ultra-low latency 3d = Reserved; Don't use
5-4	DAC_DSP_HPF_SEL[1:0]	R/W	0x1	DAC channel high-pass filter (HPF) selection. 0d = Programmable first-order IIR filter for a custom HPF with default coefficient values in P17_R120-127 and P18_R8-11 set as the all-pass filter 1d = HPF with a cutoff of 0.00002 x f_S (1 Hz at f_S = 48 kHz) is selected 2d = HPF with a cutoff of 0.00025 x f_S (12 Hz at f_S = 48 kHz) is selected 3d = HPF with a cutoff of 0.002 x f_S (96 Hz at f_S = 48 kHz) is selected
3-2	DAC_DSP_BQ_CFG[1:0]	R/W	0x2	Number of biquads per DAC channel configuration. 0d = No biquads per channel; biquads are all disabled 1d = 1 biquad per channel 2d = 2 biquads per channel 3d = 3 biquads per channel
1	DAC_DSP_DISABLE_SOFT_STEP	R/W	0x0	DAC Soft-stepping disable during DVOL change, mute, and unmute. 0d = Soft-stepping enabled 1d = Soft-stepping disabled
0	DAC_DSP_DVOL_GANG	R/W	0x0	DVOL control ganged across DAC channels. 0d = Each DAC channel has its own DVOL CTRL settings as programmed in the DAC_CHx_DVOL bits 1d = All active channels must use the channel 1 DVOL setting (DAC_CH1_DVOL) irrespective of whether channel 1 is turned on or not

7.1.97 CH_EN Register (Address = 0x76) [Reset = 0xCC]

CH_EN is shown in Figure 7-97 and described in Table 7-98.

Return to the Summary Table.

This register is the channel enable configuration register.

Figure 7-97 CH_EN Register

7	6	5	4	3	2	1	0
IN_CH1_EN	IN_CH2_EN	IN_CH3_EN	IN_CH4_EN	OUT_CH1_EN	OUT_CH2_EN	OUT_CH3_EN	OUT_CH4_EN
R/W-1b	R/W-1b	R/W-0b	R/W-0b	R/W-1b	R/W-1b	R/W-0b	R/W-0b

Table 7-98 CH_EN Register Field Descriptions

Bit	Field	Type	Reset	Description
7	IN_CH1_EN	R/W	0x1	Input channel 1 enable setting. 0d = Input channel 1 is disabled 1d = Input channel 1 is enabled
6	IN_CH2_EN	R/W	0x1	Input channel 2 enable setting. 0d = Input channel 2 is disabled 1d = Input channel 2 is enabled
5	IN_CH3_EN	R/W	0x0	Input channel 3 enable setting. 0d = Input channel 3 is disabled 1d = Input channel 3 is enabled
4	IN_CH4_EN	R/W	0x0	Input channel 4 enable setting. 0d = Input channel 4 is disabled 1d = Input channel 4 is enabled
3	OUT_CH1_EN	R/W	0x1	Output channel 1 enable setting. 0d = Output channel 1 is disabled 1d = Output channel 1 is enabled
2	OUT_CH2_EN	R/W	0x1	Output channel 2 enable setting. 0d = Output channel 2 is disabled 1d = Output channel 2 is enabled
1	OUT_CH3_EN	R/W	0x0	Output channel 3 enable setting. 0d = Output channel 3 is disabled 1d = Output channel 3 is enabled
0	OUT_CH4_EN	R/W	0x0	Output channel 4 enable setting. 0d = Output channel 4 is disabled 1d = Output channel 4 is enabled

7.1.98 DYN_PUPD_CFG Register (Address = 0x77) [Reset = 0x00]

DYN_PUPD_CFG is shown in Figure 7-98 and described in Table 7-99.

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This register is the power-up configuration register.

Figure 7-98 DYN_PUPD_CFG Register

7	6	5	4	3	2	1	0
ADC_DYN_PUPD_EN	ADC_DYN_MAXCH_SEL	DAC_DYN_PUPD_EN	DAC_DYN_MAXCH_SEL	DYN_PUPD_ADC_PDM_DIFF_CLK	RESERVED
R/W-0b	R/W-0b	R/W-0b	R/W-0b	R/W-0b	R-000b

Table 7-99 DYN_PUPD_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	ADC_DYN_PUPD_EN	R/W	0x0	Dynamic channel power-up, power-down enable for record path. 0d = Channel power-up, power-down is not supported if any channel recording is on 1d = Channel can be powered up or down individually, even if channel recording is on
6	ADC_DYN_MAXCH_SEL	R/W	0x0	Dynamic mode maximum channel select configuration for record path. 0d = Channel 1 and channel 2 are used with dynamic channel power-up, power-down feature enabled 1d = Channel 1 to channel 4 are used with dynamic channel power-up, power-down feature enabled
5	DAC_DYN_PUPD_EN	R/W	0x0	Dynamic channel power-up, power-down enable for playback path. 0d = Channel power-up, power-down is not supported if any channel playback is on 1d = Channel can be powered up or down individually, even if channel playback is on
4	DAC_DYN_MAXCH_SEL	R/W	0x0	Dynamic mode maximum channel select configuration for playback path. 0d = Channel 1 and channel 2 are used with dynamic channel power-up, power-down feature enabled 1d = Channel 1 to channel 4 are used with dynamic channel power-up, power-down feature enabled
3	DYN_PUPD_ADC_PDM_DIFF_CLK	R/W	0x0	Dynamic power-up power-down with different adc mod clock and pdm clock configuration. 0d = Same ADC MOD CLK and PDM CLK in dynamic pupd 1d = Different ADC MOD CLK and PDM CLK in dynamic pupd
2-0	RESERVED	R	0x0	Reserved bits; Write only reset value

7.1.99 PWR_CFG Register (Address = 0x78) [Reset = 0x00]

PWR_CFG is shown in Figure 7-99 and described in Table 7-100.

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This register is the power-up configuration register.

Figure 7-99 PWR_CFG Register

7	6	5	4	3	2	1	0
ADC_PDZ	DAC_PDZ	MICBIAS_PDZ	RESERVED	UAD_EN	VAD_EN	UAG_EN	RESERVED
R/W-0b	R/W-0b	R/W-0b	R-0b	R/W-0b	R/W-0b	R/W-0b	R-0b

Table 7-100 PWR_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	ADC_PDZ	R/W	0x0	Power control for ADC and PDM channels. 0d = Power down all ADC and PDM channels 1d = Power up all enabled ADC and PDM channels
6	DAC_PDZ	R/W	0x0	Power control for DAC channels. 0d = Power down all DAC channels 1d = Power up all enabled DAC channels
5	MICBIAS_PDZ	R/W	0x0	Power control for MICBIAS. 0d = Power down MICBIAS 1d = Power up MICBIAS
4	RESERVED	R	0x0	Reserved bit; Write only reset value
3	UAD_EN	R/W	0x0	Enable ultrasound activity detection (UAD) algorithm. 0d = UAD is disabled 1d = UAD is enabled
2	VAD_EN	R/W	0x0	Enable voice activity detection (VAD) algorithm. 0d = VAD is disabled 1d = VAD is enabled
1	UAG_EN	R/W	0x0	Enable ultrasound activity detection (UAG) algorithm. 0d = UAG is disabled 1d = UAG is enabled
0	RESERVED	R	0x0	Reserved bit; Write only reset value

7.1.100 DEV_STS0 Register (Address = 0x79) [Reset = 0x00]

DEV_STS0 is shown in Figure 7-100 and described in Table 7-101.

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This register is the device status value register 0.

Figure 7-100 DEV_STS0 Register

7	6	5	4	3	2	1	0
IN_CH1_STATUS	IN_CH2_STATUS	IN_CH3_STATUS	IN_CH4_STATUS	OUT_CH1_STATUS	OUT_CH2_STATUS	OUT_CH3_STATUS	OUT_CH4_STATUS
R-0b	R-0b	R-0b	R-0b	R-0b	R-0b	R-0b	R-0b

Table 7-101 DEV_STS0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	IN_CH1_STATUS	R	0x0	ADC or PDM channel 1 power status. 0d = ADC or PDM channel is powered down 1d = ADC or PDM channel is powered up
6	IN_CH2_STATUS	R	0x0	ADC or PDM channel 2 power status. 0d = ADC or PDM channel is powered down 1d = ADC or PDM channel is powered up
5	IN_CH3_STATUS	R	0x0	ADC or PDM channel 1 power status. 0d = ADC or PDM channel is powered down 1d = ADC or PDM channel is powered up
4	IN_CH4_STATUS	R	0x0	ADC or PDM channel 2 power status. 0d = ADC or PDM channel is powered down 1d = ADC or PDM channel is powered up
3	OUT_CH1_STATUS	R	0x0	DAC channel 1 power status. 0d = DAC channel is powered down 1d = DAC channel is powered up
2	OUT_CH2_STATUS	R	0x0	DAC channel 2 power status. 0d = DAC channel is powered down 1d = DAC channel is powered up
1	OUT_CH3_STATUS	R	0x0	DAC channel 3 power status. 0d = DAC channel is powered down 1d = DAC channel is powered up
0	OUT_CH4_STATUS	R	0x0	DAC channel 4 power status. 0d = DAC channel is powered down 1d = DAC channel is powered up

7.1.101 DEV_STS1 Register (Address = 0x7A) [Reset = 0x80]

DEV_STS1 is shown in Figure 7-101 and described in Table 7-102.

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This register is the device status value register 1.

Figure 7-101 DEV_STS1 Register

7	6	5	4	3	2	1	0
MODE_STS[2:0]			PLL_STS	MICBIAS_STS	BOOST_STS	CHx_PD_FLT_STS	ALL_CHx_PD_FLT_STS
R-100b			R-0b	R-0b	R-0b	R-0b	R-0b

Table 7-102 DEV_STS1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-5	MODE_STS[2:0]	R	0x4	Device mode status. 0-3d = Reserved 4d = Device is in sleep mode or software shutdown mode 5d = Reserved 6d = Device is in active mode with all record and playback channels turned off 7d = Device is in active mode with at least one record or playback channel turned on
4	PLL_STS	R	0x0	PLL status. 0d = PLL is not enabled 1d = PLL is enabled
3	MICBIAS_STS	R	0x0	MICBIAS status. 0d = MICBIAS is disabled 1d = MICBIAS is enabled
2	BOOST_STS	R	0x0	Boost status. 0d = Boost is disabled 1d = Boost is enabled
1	CHx_PD_FLT_STS	R	0x0	Status for PD on INxx Analog inputs faults 0d = No ADC Channel is Powered Down due to fault/s on Analog inputs INxx 1d = Some ADC Channel is Powered Down due to fault/s on Analog inputs INxx
0	ALL_CHx_PD_FLT_STS	R	0x0	Status for PD on Micbias faults 0d = No ADC Channel is Powered Down due to fault/s related to Micbias 1d = All ADC Channels are Powered Down due to fault/s related to Micbias

7.1.102 I2C_CKSUM Register (Address = 0x7E) [Reset = 0x00]

I2C_CKSUM is shown in Figure 7-102 and described in Table 7-103.

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This register returns the I²C transactions checksum value.

Figure 7-102 I2C_CKSUM Register

7	6	5	4	3	2	1	0
I2C_CKSUM[7:0]
R/W-00000000b

Table 7-103 I2C_CKSUM Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	I2C_CKSUM[7:0]	R/W	0x0	These bits return the I²C transactions checksum value. Writing to this register resets the checksum to the written value. This register is updated on writes to other registers on all pages.