ZHCSN44B December   2021  – December 2023 SN75LVPE5421

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 DC Electrical Characteristics
    6. 5.6 High Speed Electrical Characteristics
    7. 5.7 SMBUS/I2C Timing Characteristics
    8. 5.8 Typical Characteristics
    9. 5.9 Typical Jitter Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Five-Level Control Inputs
      2. 6.3.2 Linear Equalization
      3. 6.3.3 Flat Gain
      4. 6.3.4 Receiver Detect State Machine
    4. 6.4 Device Functional Modes
      1. 6.4.1 Active PCIe Mode
      2. 6.4.2 Active Buffer Mode
      3. 6.4.3 Standby Mode
    5. 6.5 Programming
      1. 6.5.1 Pin Mode
      2. 6.5.2 SMBUS/I2C Register Control Interface
        1. 6.5.2.1 Shared Registers
        2. 6.5.2.2 Channel Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 PCIe x8 Lane Switching
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
      2. 7.2.2 Protocol Agnostic Linear Redriver for High Speed Interfaces
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 接收文档更新通知
    2. 8.2 支持资源
    3. 8.3 Trademarks
    4. 8.4 静电放电警告
    5. 8.5 术语表
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

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  • RUA|42
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6.5.2.2 Channel Registers

Table 6-9 RX Detect Status Register (Channel Register Base + Offset = 0x00)
Bit Field Type Reset Description
7 RX_det_comp_p R 0x0 RX Detect positive data pin status:

0: Not detected

1: Detected – the value is latched
6 RX_det_comp_n R 0x0 RX Detect negative data pin status:

0: Not detected

1: Detected – the value is latched
5-0 RESERVED R 0x0 Reserved
Table 6-10 EQ Gain Control Register (Channel Register Base + Offset = 0x01)
Bit Field Type Reset Description
7 eq_stage1_bypass R/W 0x0

Enable EQ stage 1 bypass:

0: Bypass disabled

1: Bypass enabled
6 eq_stage1_3 R/W 0x0

EQBoost stage 1 control

See Table 6-2 for details
5 eq_stage1_2 R/W 0x0
4 eq_stage1_1 R/W 0x0
3 eq_stage1_0 R/W 0x0
2 eq_stage2_2 R/W 0x0

EQ Boost stage 2 control

See Table 6-2 for details
1 eq_stage2_1 R/W 0x0
0 eq_stage2_0 R/W 0x0
Table 6-11 EQ Gain / Flat Gain Control Register (Channel Register Base + Offset = 0x03)
Bit Field Type Reset Description
7 RESERVED R 0x0 Reserved
6 eq_profile_3 R/W 0x0

EQ mid-frequency boost profile

See Table 6-2 for details

5 eq_profile_2 R/W 0x0
4 eq_profile_1 R/W 0x0
3 eq_profile_0 R/W 0x0
2 flat_gain_2 R/W 0x1

Flat gain select:

See Table 6-3 for details

1 flat_gain_1 R/W 0x0
0 flat_gain_0 R/W 0x1
Table 6-12 RX Detect Control Register (Channel Register Base + Offset = 0x04)
Bit Field Type Reset Description
7-3 RESERVED R 0x0 Reserved
2 mr_RX_det_man R/W 0x0

Manual override of RX_detect_p/n decision:

0: RX detect state machine is enabled

1: RX detect state machine is overridden – always valid RX termination detected
1 en_RX_det_count R/W 0x0 Enable additional RX detect polling

0: Additional RX detect polling disabled

1: Additional RX detect polling enabled
0 sel_RX_det_count R/W 0x0

Select number of valid RX detect polls – gated by en_RX_det_count = 1

0: Device transmitters poll until 2 consecutive valid detections

1: Device transmitters poll until 3 consecutive valid detections
Table 6-13 PD Override Register (Channel Register Base + Offset = 0x05)
Bit Field Type Reset Description
7 device_en_override R/W 0x0 Enable power down overrides through SMBus/I2C

0: Manual override disabled

1: Manual override enabled
6-0 device_en R/W 0x111111 Manual power down of redriver various blocks – gated by device_en_override = 1

111111: All blocks are enabled

000000: All blocks are disabled
Table 6-14 RX Detect Reset Register (Channel Register Base + Offset = 0x0A)
Bit Field Type Reset Description
7-3 RESERVED R 0x0 Reserved
2 mr_RX_det_rst R/W 0x0

RX Detect state machine reset. Toggle the bit if RX Detect machine needs to be reset in I2C mode

0: state machine is not reset

1: RX detect state machine is reset
1-0 RESERVED R/W 0x0 Reserved