SLLS980E June   2009  – November 2016 SN75LVDS83A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Dissipation Ratings
    7. 7.7 Timing Requirements
    8. 7.8 Switching Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 TTL Input Data
      2. 9.3.2 LVDS Output Data
    4. 9.4 Device Functional Modes
      1. 9.4.1 Input Clock Edge
      2. 9.4.2 Low Power Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Signal Connectivity
      2. 10.1.2 PCB Routing
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Power Up Sequence
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Board Stackup
      2. 12.1.2 Power and Ground Planes
      3. 12.1.3 Traces, Vias, and Other PCB Components
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Pin Configuration and Functions

DGG Package
56-Pin TSSOP
Top View
SN75LVDS83A po_dgg_lls980.gif

Pin Functions

PIN TYPE(1) DESCRIPTION
NAME NO.
CLKIN 31 I CMOS with pulldown; input pixel clock; rising or falling clock polarity is selectable by Control input CLKSEL.
CLKOUTM 40 O Differential LVDS pixel clock output.
Output is high-impedance when SHTDN is pulled low (de-asserted).
CLKOUTP 39 O
CLKSEL 17 I CMOS with pulldown; selects between rising edge input clock trigger (CLKSEL = VIH) and falling edge input clock trigger (CLKSEL = VIL).
D0 51 I CMOS with pulldown; data inputs. To connect a graphic source successfully to a display, the bit assignment of D[27:0] is critical (and not necessarily intuitive).
For input bit assignment, see Figure 14 to Figure 17 for details.
Note: if application only requires 18-bit color, connect unused inputs D5, D10, D11, D16, D17, D23, and D27 to GND.
D1 52 I
D2 54 I
D3 55 I
D4 56 I
D5 2 I
D6 3 I
D7 4 I
D8 6 I
D9 7 I
D10 8 I
D11 10 I
D12 11 I
D13 12 I
D14 14 I
D15 15 I
D16 16 I
D17 18 I
D18 19 I
D19 20 I
D20 22 I
D21 23 I
D22 24 I
D23 25 I
D24 27 I
D25 28 I
D26 30 I
D27 50 I
GND 5, 23, 21, 29,
43, 49, 53		 P Supply ground for VCC, LVDSVCC, and PLLVCC(2)
LVDSVCC 44 P 3.3-V LVDS output analog supply(2)
PLLVCC 34 P 3.3-V PLL analog supply(2)
SHTDN 32 I CMOS with pulldown; device shut down; pull low (deassert) to shut down the device (low power, resets all registers) and high (assert) for normal operation.
VCC 1, 9, 26 P 3.3-V digital supply voltage(2)
Y0M 48 O Differential LVDS data outputs. Output is high-impedance when SHTDN is pulled low (deasserted).
Y0P 47 O Differential LVDS data outputs. Output is high-impedance when SHTDN is pulled low (deasserted).
Y1M 46 O Differential LVDS data outputs. Output is high-impedance when SHTDN is pulled low (deasserted).
Y1P 45 O Differential LVDS data outputs. Output is high-impedance when SHTDN is pulled low (deasserted).
Y2M 42 O Differential LVDS data outputs. Output is high-impedance when SHTDN is pulled low (deasserted).
Y2P 41 O Differential LVDS data outputs. Output is high-impedance when SHTDN is pulled low (deasserted).
Y3M 38 O Differential LVDS Data outputs. Output is high-impedance when SHTDN is pulled low (deasserted).
Note: If the application only requires 18-bit color, this output can be left open.
Y3P 37 O Differential LVDS Data outputs. Output is high-impedance when SHTDN is pulled low (deasserted).
Note: If the application only requires 18-bit color, this output can be left open.
(1) I = Input, O = Output, P = Power
(2) For a multi-layer PCB, TI recommends keeping one common GND layer underneath the device and connecting all ground terminals directly to this plane.