SLLS980E June   2009  – November 2016 SN75LVDS83A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Dissipation Ratings
    7. 7.7 Timing Requirements
    8. 7.8 Switching Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 TTL Input Data
      2. 9.3.2 LVDS Output Data
    4. 9.4 Device Functional Modes
      1. 9.4.1 Input Clock Edge
      2. 9.4.2 Low Power Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Signal Connectivity
      2. 10.1.2 PCB Routing
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Power Up Sequence
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Board Stackup
      2. 12.1.2 Power and Ground Planes
      3. 12.1.3 Traces, Vias, and Other PCB Components
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

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8 Parameter Measurement Information

SN75LVDS83A set_hold_lls846.gif
All input timing is defined at IOVDD / 2 on an input signal with a 10% to 90% rise or fall time of less than 3 ns. CLKSEL = 0 V.
Figure 5. Set Up and Hold Time Definition
SN75LVDS83A test_load_lls846.gif Figure 6. Test Load and Voltage Definitions for LVDS Outputs
SN75LVDS83A gray_scale_lls846.gif
The 16 grayscale test pattern test device power consumption for a typical display pattern.
Figure 7. 16 Grayscale Test Pattern
SN75LVDS83A worst_case_lls846.gif
The worst-case test pattern produces nearly the maximum switching frequency for all of the LVDS outputs.
Figure 8. Worst-Case Power Test Pattern
SN75LVDS83A timing_lls846.gif
CLKOUT is shown with CLKSEL at high-level.
CLKIN polarity depends on CLKSEL input level.
Figure 9. SN75LVDS83A Timing Definitions
SN75LVDS83A out_clock_lls846.gif Figure 10. Output Clock Jitter Test Set Up
SN75LVDS83A enable_time_lls846.gif Figure 11. Enable Time Waveforms
SN75LVDS83A disable_time_lls846.gif Figure 12. Disable Time Waveforms