SLLSE12A November   2009  – July 2014 SN75DP119

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Pre-Emphasis and VOD Output Swing Setings
    4. 9.4 Device Functional Modes
      1. 9.4.1 Status Detect and Operating Modes Flow Diagram
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Trademarks
    2. 13.2 Electrostatic Discharge Caution
    3. 13.3 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

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10 Application and Implementation

10.1 Application Information

Figure 9 provides a simple schematic reference for the 14-pin package. In addition to this schematic sufficient VCC decoupling for the 3.3V power supply is necessary.

10.2 Typical Application

sch_llse12.gifFigure 9. Simplified Schematic drawing

10.2.1 Design Requirements

For this design example, use the following as the input parameters.

Table 3. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
VCC 3.3 V
Main Link Input Voltage VID = 0.15 to 1.4 Vpp
Control Pin Max Voltage for Low 0.5 V
Control Pin Voltage Range Mid Min (VCC/2) - 0.3 V to Max of (VCC/2) + 0.3 V
Control Pin Min Voltage for High Min VCC - 0.5 V
Main Link AC Decoupling Cap 75 nF to 200 nF Recommend 100 nF

10.2.2 Detailed Design Procedure

  • Determine the output swing of the Graphic Processing Unit (GPU) .
  • Determine the loss profile between the GPU and the LCD display connector.
  • Determine the loss profile between the mother board LCD display connector and the DisplayPort receiver.
  • Determine the DisplayPort receiver capabilities, acceptable VID along with its receive equalizer capability.
  • Based upon this loss profile and signal swing determine optimal location for the SN75DP119, close to the connector, midway, or close to GPU.
  • Use the typical application drawing, Figure 9, for information on using the AC coupling caps and control pin resistors.
  • Set the DP119 Input equalizer appropriately to support the loss profile and signal swing for the link between the GPU and connector by using the EQ_CTL control pin.
  • Set the DP119 VOD and Pre-emphasis level appropriately to support the Connector to DisplayPort receiver link by using the PRE_CTL and VOC_CTL control pins.
  • The thermal pad must be connected to ground.
  • Use a 1 µF and 0.1 µF decouple caps from VCC pins to Ground.

10.2.3 Application Curves

eye_pat_llse12.gif
DR = 2.7 Gbps VOD = 400 mVpp PRE = 0 dB
Figure 10. Eye Pattern Output To DP119
eye2_pat_llse12.gif
DR = 2.7 Gbps VOD = 400 mVpp PRE = 0 dB
Figure 11. Eye Pattern Output To DP119