SCLS805 June   2020 SN74HCS596-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Benefits of Schmitt-trigger Inputs
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Characteristics
    7. 6.7 Switching Characteristics
    8. 6.8 Operating Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Balanced CMOS Push-Pull Outputs
      2. 8.3.2 CMOS Open-Drain Outputs
      3. 8.3.3 CMOS Schmitt-Trigger Inputs
      4. 8.3.4 Positive and Negative Clamping Diodes
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Power Considerations
        2. 9.2.1.2 Input Considerations
        3. 9.2.1.3 Output Considerations
        4. 9.2.1.4 Timing Considerations
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Documentation Support
        1. 12.1.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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5 Pin Configuration and Functions

D and PW
16-Pin SOIC and TSSOP
Top View
SN74HCS596-Q1 pw-pinout-diagram-qbqc.gif

Pin Functions

PIN TYPE DESCRIPTION
NAME NO.
QB 1 Output QB output (open-drain)
QC 2 Output QC output (open-drain)
QD 3 Output QD output (open-drain)
QE 4 Output QE output (open-drain)
QF 5 Output QF output (open-drain)
QG 6 Output QG output (open-drain)
QH 7 Output QH output (open-drain)
GND 8 — Ground
QH' 9 Output Serial output, can be used for cascading (push-pull)
SRCLR 10 Input Shift register clear, active low
SRCLK 11 Input Shift register clock, rising edge triggered
RCLK 12 Input Output register clock, rising edge triggered
OE 13 Input Output Enable, active low
SER 14 Input Serial input
QA 15 Output QA output (open-drain)
VCC 16 — Positive supply