ZHCSP26A october   2021  – december 2022 SN74HCS373

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
    1.     5
    2.     6
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
    1.     9
    2.     Pin Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Characteristics
    7.     18
    8. 6.7 Switching Characteristics
    9. 6.8 Operating Characteristics
    10. 6.9 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Balanced CMOS 3-State Outputs
      2. 8.3.2 CMOS Schmitt-Trigger Inputs
      3. 8.3.3 Clamp Diode Structure
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Power Considerations
        2. 9.2.1.2 输入注意事项
        3. 9.2.1.3 Output Considerations
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 接收文档更新通知
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 静电放电警告
    6. 12.6 术语表
  14. 13Mechanical, Packaging, and Orderable Information

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7 Parameter Measurement Information

Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 2.5 ns.

For clock inputs, fmax is measured when the input duty cycle is 50%.

The outputs are measured one at a time with one input transition per measurement.

GUID-C26C5B57-52C4-45A5-99AA-2B2EDEC9E40F-low.gif
(1) CL includes probe and test-fixture capacitance.
Figure 7-1 Load Circuit for 3-State Outputs
GUID-7FBFF776-CCD5-45F1-9468-A64F1D560BB5-low.gifFigure 7-3 Voltage Waveforms, Setup and Hold Times
GUID-B66D4D5F-A783-4DA6-BE42-21A7D33CE0DE-low.gifFigure 7-5 Voltage Waveforms Propagation Delays
GUID-79D10B94-1B94-4919-A243-405EA38DB8C6-low.gifFigure 7-2 Voltage Waveforms, Pulse Duration
GUID-D62636E0-966A-445C-9725-447DD11AB795-low.gif
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 7-4 Voltage Waveforms Propagation Delays
GUID-7A99E510-476E-40DE-90AB-833DE213EF8F-low.gif
(1) The greater between tr and tf is the same as tt.
Figure 7-6 Voltage Waveforms, Input and Output Transition Times